This patch drops the coreboot CMOS checksum ranges from Kconfig because
[coreboot.git] / src / mainboard / amd / serengeti_cheetah_fam10 / Kconfig
1 config BOARD_AMD_SERENGETI_CHEETAH_FAM10
2         bool "Serengeti Cheetah (Fam10)"
3         select ARCH_X86
4         select CPU_AMD_SOCKET_F_1207
5         select NORTHBRIDGE_AMD_AMDFAM10
6         select NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX
7         select SOUTHBRIDGE_AMD_AMD8111
8         select SOUTHBRIDGE_AMD_AMD8132
9         select SUPERIO_WINBOND_W83627HF
10         select BOARD_HAS_FADT
11         select HAVE_BUS_CONFIG
12         select HAVE_PIRQ_TABLE
13         select HAVE_MP_TABLE
14         select USE_PRINTK_IN_CAR
15         select USE_DCACHE_RAM
16         select HAVE_HARD_RESET
17         select SB_HT_CHAIN_UNITID_OFFSET_ONLY
18         select SERIAL_CPU_INIT
19         select AMDMCT
20         select HAVE_ACPI_TABLES
21         select BOARD_ROMSIZE_KB_1024
22         select ENABLE_APIC_EXT_ID
23         select LIFT_BSP_APIC_ID
24         select TINY_BOOTBLOCK
25
26 config MAINBOARD_DIR
27         string
28         default amd/serengeti_cheetah_fam10
29         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
30
31 config APIC_ID_OFFSET
32         hex
33         default 0x0
34         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
35
36 config MAINBOARD_PART_NUMBER
37         string
38         default "Serengeti Cheetah (Fam10)"
39         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
40
41 config HW_MEM_HOLE_SIZEK
42         hex
43         default 0x100000
44         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
45
46 # 6 * MAX_PHYSICAL_CPUS
47 config MAX_CPUS
48         int
49         default 48
50         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
51
52 config MAX_PHYSICAL_CPUS
53         int
54         default 8
55         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
56
57 config HW_MEM_HOLE_SIZE_AUTO_INC
58         bool
59         default n
60         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
61
62 config MEM_TRAIN_SEQ
63         int
64         default 2
65         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
66
67 config SB_HT_CHAIN_ON_BUS0
68         int
69         default 2
70         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
71
72 config HT_CHAIN_END_UNITID_BASE
73         hex
74         default 0x6
75         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
76
77 config HT_CHAIN_UNITID_BASE
78         hex
79         default 0xa
80         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
81
82 config USE_INIT
83         bool
84         default n
85         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
86
87 config IRQ_SLOT_COUNT
88         int
89         default 11
90         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
91
92 config AMD_UCODE_PATCH_FILE
93         string
94         default "mc_patch_01000095.h"
95         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
96
97 config RAMTOP
98         hex
99         default 0x1000000
100         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
101
102 config HEAP_SIZE
103         hex
104         default 0xc0000
105         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
106
107 config ACPI_SSDTX_NUM
108         int
109         default 5
110         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
111
112 config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
113         hex
114         default 0x2b80
115         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
116
117 config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
118         hex
119         default 0x1022
120         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
121
122 config RAMBASE
123         hex
124         default 0x200000
125         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10
126
127 config ID_SECTION_OFFSET
128         hex
129         default 0x80
130         depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10