src/mainboard/amd/serengeti_cheetah_fam10/Config.lb

   1 #
   2 # This file is part of the LinuxBIOS project.
   3 #
   4 # Copyright (C) 2007 Advanced Micro Devices, Inc.
   5 #
   6 # This program is free software; you can redistribute it and/or modify
   7 # it under the terms of the GNU General Public License as published by
   8 # the Free Software Foundation; version 2 of the License.
   9 #
  10 # This program is distributed in the hope that it will be useful,
  11 # but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.   See the
  13 # GNU General Public License for more details.
  14 #
  15 # You should have received a copy of the GNU General Public License
  16 # along with this program; if not, write to the Free Software
  17 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18 #
  19
  20 ##
  21 ## Compute the location and size of where this firmware image
  22 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
  23 ##
  24 if USE_FAILOVER_IMAGE
  25         default ROM_SECTION_SIZE   = FAILOVER_SIZE
  26         default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
  27 else
  28     if USE_FALLBACK_IMAGE
  29         default ROM_SECTION_SIZE   = FALLBACK_SIZE
  30         default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
  31     else
  32         default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
  33         default ROM_SECTION_OFFSET = 0
  34     end
  35 end
  36
  37 ##
  38 ## Compute the start location and size size of
  39 ## The linuxBIOS bootloader.
  40 ##
  41 default PAYLOAD_SIZE             = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
  42 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
  43
  44 ##
  45 ## Compute where this copy of linuxBIOS will start in the boot rom
  46 ##
  47 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
  48
  49 ##
  50 ## Compute a range of ROM that can cached to speed up linuxBIOS,
  51 ## execution speed.
  52 ##
  53 ## XIP_ROM_SIZE must be a power of 2.
  54 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
  55 ##
  56 default XIP_ROM_SIZE=65536
  57 #
  58 if USE_FAILOVER_IMAGE
  59         default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
  60 else
  61     if USE_FALLBACK_IMAGE
  62         default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
  63     else
  64         default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
  65     end
  66 end
  67
  68 arch i386 end
  69
  70 ##
  71 ## Build the objects we have code for in this directory.
  72 ##
  73
  74 driver mainboard.o
  75
  76
  77 #needed by irq_tables and mptable and acpi_tables
  78 object get_bus_conf.o
  79
  80 if HAVE_MP_TABLE
  81         object mptable.o
  82 end
  83
  84 if HAVE_PIRQ_TABLE
  85         object irq_tables.o
  86 end
  87
  88 if HAVE_ACPI_TABLES
  89          object acpi_tables.o
  90          object fadt.o
  91         makerule dsdt.c
  92                 depends "$(MAINBOARD)/dx/dsdt_lb.dsl"
  93                 action  "iasl -p $(PWD)/dsdt_lb -tc $(MAINBOARD)/dx/dsdt_lb.dsl"
  94                 action  "mv dsdt_lb.hex dsdt.c"
  95         end
  96          object ./dsdt.o
  97
  98         #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
  99
 100         if ACPI_SSDTX_NUM
 101         makerule ssdt2.c
 102                 depends "$(MAINBOARD)/dx/pci2.asl"
 103                 action  "iasl -p $(PWD)/pci2 -tc $(MAINBOARD)/dx/pci2.asl"
 104                 action  "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex"
 105                 action  "mv pci2.hex ssdt2.c"
 106         end
 107         object ./ssdt2.o
 108         makerule ssdt3.c
 109                 depends "$(MAINBOARD)/dx/pci3.asl"
 110                 action  "iasl -p $(PWD)/pci3 -tc $(MAINBOARD)/dx/pci3.asl"
 111                 action  "perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex"
 112                 action  "mv pci3.hex ssdt3.c"
 113         end
 114         object ./ssdt3.o
 115         makerule ssdt4.c
 116                 depends "$(MAINBOARD)/dx/pci4.asl"
 117                 action  "iasl -p $(PWD)/pci4 -tc $(MAINBOARD)/dx/pci4.asl"
 118                 action  "perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex"
 119                 action  "mv pci4.hex ssdt4.c"
 120         end
 121         object ./ssdt4.o
 122         makerule ssdt5.c
 123                 depends "$(MAINBOARD)/dx/pci5.asl"
 124                 action  "iasl -p $(PWD)/pci5 -tc $(MAINBOARD)/dx/pci5.asl"
 125                 action  "perl -pi -e 's/AmlCode/AmlCode_ssdt5/g' pci5.hex"
 126                 action  "mv pci5.hex ssdt5.c"
 127         end
 128         object ./ssdt5.o
 129          end
 130 end
 131
 132 if USE_DCACHE_RAM
 133         makedefine CACHE_AS_RAM_AUTO_C:=cache_as_ram_auto.c
 134
 135         if CONFIG_USE_INIT
 136                 # compile cache_as_ram.c to auto.o
 137                 makerule ./cache_as_ram_auto.o
 138                         depends "$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) option_table.h"
 139                         action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
 140                 end
 141
 142         else
 143                 #compile cache_as_ram.c to auto.inc
 144                 makerule ./cache_as_ram_auto.inc
 145                         depends "$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) option_table.h"
 146                         action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
 147                         action "perl -e 's/.rodata/.rom.data/g' -pi $@"
 148                         action "perl -e 's/.text/.section .rom.text/g' -pi $@"
 149                 end
 150
 151         end
 152 end
 153
 154 if USE_FAILOVER_IMAGE
 155 else
 156     if CONFIG_AP_CODE_IN_CAR
 157          makerule ./apc_auto.o
 158                  depends "$(MAINBOARD)/apc_auto.c option_table.h"
 159                  action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
 160          end
 161          ldscript /arch/i386/init/ldscript_apc.lb
 162     end
 163 end
 164
 165 ##
 166 ## Build our 16 bit and 32 bit linuxBIOS entry code
 167 ##
 168
 169 if HAVE_FAILOVER_BOOT
 170     if USE_FAILOVER_IMAGE
 171         mainboardinit cpu/x86/16bit/entry16.inc
 172         ldscript /cpu/x86/16bit/entry16.lds
 173     end
 174 else
 175     if USE_FALLBACK_IMAGE
 176         mainboardinit cpu/x86/16bit/entry16.inc
 177         ldscript /cpu/x86/16bit/entry16.lds
 178     end
 179 end
 180
 181 mainboardinit cpu/x86/32bit/entry32.inc
 182 if USE_DCACHE_RAM
 183          if CONFIG_USE_INIT
 184                  ldscript /cpu/x86/32bit/entry32.lds
 185          end
 186
 187          if CONFIG_USE_INIT
 188                  ldscript /cpu/amd/car/cache_as_ram.lds
 189          end
 190 end
 191
 192 ##
 193 ## Build our reset vector (This is where linuxBIOS is entered)
 194 ##
 195 if HAVE_FAILOVER_BOOT
 196     if USE_FAILOVER_IMAGE
 197         mainboardinit cpu/x86/16bit/reset16.inc
 198         ldscript /cpu/x86/16bit/reset16.lds
 199     else
 200         mainboardinit cpu/x86/32bit/reset32.inc
 201         ldscript /cpu/x86/32bit/reset32.lds
 202     end
 203 else
 204     if USE_FALLBACK_IMAGE
 205         mainboardinit cpu/x86/16bit/reset16.inc
 206         ldscript /cpu/x86/16bit/reset16.lds
 207     else
 208         mainboardinit cpu/x86/32bit/reset32.inc
 209         ldscript /cpu/x86/32bit/reset32.lds
 210     end
 211 end
 212
 213
 214 ##
 215 ## Include an id string (For safe flashing)
 216 ##
 217 mainboardinit arch/i386/lib/id.inc
 218 ldscript /arch/i386/lib/id.lds
 219
 220 if USE_DCACHE_RAM
 221         ##
 222         ## Setup Cache-As-Ram
 223         ##
 224         mainboardinit cpu/amd/car/cache_as_ram.inc
 225 end
 226
 227 ###
 228 ### This is the early phase of linuxBIOS startup
 229 ### Things are delicate and we test to see if we should
 230 ### failover to another image.
 231 ###
 232 if HAVE_FAILOVER_BOOT
 233     if USE_FAILOVER_IMAGE
 234         if USE_DCACHE_RAM
 235                 ldscript /arch/i386/lib/failover_failover.lds
 236         end
 237     end
 238 else
 239     if USE_FALLBACK_IMAGE
 240         if USE_DCACHE_RAM
 241                 ldscript /arch/i386/lib/failover.lds
 242         end
 243     end
 244 end
 245
 246 ###
 247 ### O.k. We aren't just an intermediary anymore!
 248 ###
 249
 250 ##
 251 ## Setup RAM
 252 ##
 253 if USE_DCACHE_RAM
 254
 255         if CONFIG_USE_INIT
 256                 initobject cache_as_ram_auto.o
 257         else
 258                 mainboardinit ./cache_as_ram_auto.inc
 259         end
 260
 261 end
 262
 263 ##
 264 ## Include the secondary Configuration files
 265 ##
 266 if CONFIG_CHIP_NAME
 267         config chip.h
 268 end
 269
 270 dir /southbridge/amd/amd8151
 271
 272 # sample config for amd/serengeti_cheetah_fam10
 273 chip northbridge/amd/amdfam10/root_complex
 274         device apic_cluster 0 on
 275                 chip cpu/amd/socket_F_1207  #L1 and DDR2
 276                          device apic 0 on end
 277                 end
 278         end
 279         device pci_domain 0 on
 280                 chip northbridge/amd/amdfam10
 281                         device pci 18.0 on #  northbridge
 282                                 #  devices on link 0, link 0 == LDT 0
 283                                 chip southbridge/amd/amd8132
 284                                         # the on/off keyword is mandatory
 285                                         device pci 0.0 on end
 286                                         device pci 0.1 on end
 287                                         device pci 1.0 on end
 288                                         device pci 1.1 on end
 289                                 end
 290                                 chip southbridge/amd/amd8111
 291                                         # this "device pci 0.0" is the parent the next one
 292                                         # PCI bridge
 293                                         device pci 0.0 on
 294                                                 device pci 0.0 on end
 295                                                 device pci 0.1 on end
 296                                                 device pci 0.2 off end
 297                                                 device pci 1.0 off end
 298                                         end
 299                                         device pci 1.0 on
 300                                                 chip superio/winbond/w83627hf
 301                                                         device pnp 2e.0 off #  Floppy
 302                                                                 io 0x60 = 0x3f0
 303                                                                 irq 0x70 = 6
 304                                                                 drq 0x74 = 2
 305                                                         end
 306                                                         device pnp 2e.1 off #  Parallel Port
 307                                                                 io 0x60 = 0x378
 308                                                                 irq 0x70 = 7
 309                                                         end
 310                                                         device pnp 2e.2 on #  Com1
 311                                                                 io 0x60 = 0x3f8
 312                                                                 irq 0x70 = 4
 313                                                         end
 314                                                         device pnp 2e.3 off #  Com2
 315                                                                 io 0x60 = 0x2f8
 316                                                                 irq 0x70 = 3
 317                                                         end
 318                                                         device pnp 2e.5 on #  Keyboard
 319                                                                 io 0x60 = 0x60
 320                                                                 io 0x62 = 0x64
 321                                                                 irq 0x70 = 1
 322                                                                 irq 0x72 = 12
 323                                                         end
 324                                                         device pnp 2e.6 off #  CIR
 325                                                                 io 0x60 = 0x100
 326                                                         end
 327                                                         device pnp 2e.7 off #  GAME_MIDI_GIPO1
 328                                                                 io 0x60 = 0x220
 329                                                                 io 0x62 = 0x300
 330                                                                 irq 0x70 = 9
 331                                                         end
 332                                                         device pnp 2e.8 off end #  GPIO2
 333                                                         device pnp 2e.9 off end #  GPIO3
 334                                                         device pnp 2e.a off end #  ACPI
 335                                                         device pnp 2e.b on #  HW Monitor
 336                                                                 io 0x60 = 0x290
 337                                                                 irq 0x70 = 5
 338                                                         end
 339                                                 end
 340                                         end
 341                                         device pci 1.1 on end
 342                                         device pci 1.2 on end
 343                                         device pci 1.3 on
 344                                                 chip drivers/i2c/i2cmux2 # pca9556 smbus mux
 345                                                 chip drivers/i2c/i2cmux2 # pca9556 smbus mux
 346                                                         device i2c 18 on #0 pca9516 1
 347                                                                 chip drivers/generic/generic #dimm 0-0-0
 348                                                                         device i2c 50 on end
 349                                                                 end
 350                                                                 chip drivers/generic/generic #dimm 0-0-1
 351                                                                         device i2c 51 on end
 352                                                                 end
 353                                                                 chip drivers/generic/generic #dimm 0-1-0
 354                                                                         device i2c 52 on end
 355                                                                 end
 356                                                                 chip drivers/generic/generic #dimm 0-1-1
 357                                                                         device i2c 53 on end
 358                                                                 end
 359                                                         end
 360                                                         device i2c 18 on #1 pca9516 2
 361                                                                 chip drivers/generic/generic #dimm 1-0-0
 362                                                                         device i2c 50 on end
 363                                                                 end
 364                                                                 chip drivers/generic/generic #dimm 1-0-1
 365                                                                         device i2c 51 on end
 366                                                                 end
 367                                                                 chip drivers/generic/generic #dimm 1-1-0
 368                                                                         device i2c 52 on end
 369                                                                 end
 370                                                                 chip drivers/generic/generic #dimm 1-1-1
 371                                                                         device i2c 53 on end
 372                                                                 end
 373                                                         end
 374                                                 end
 375                                                 end
 376                                         end # acpi
 377                                         device pci 1.5 off end
 378                                         device pci 1.6 off end
 379                                         register "ide0_enable" = "1"
 380                                         register "ide1_enable" = "1"
 381                                 end
 382                         end #  device pci 18.0
 383
 384                         device pci 18.0 on end
 385                         device pci 18.0 on end
 386                         device pci 18.1 on end
 387                         device pci 18.2 on end
 388                         device pci 18.3 on end
 389                         device pci 18.4 on end
 390 #                       device pci 00.5 on end
 391                 end
 392         end #pci_domain
 393         #for node 32 to node 63
 394 #       device pci_domain 0 on
 395 #               chip northbridge/amd/amdfam10
 396 #                         device pci 00.0 on end#  northbridge
 397 #                         device pci 00.0 on end
 398 #                         device pci 00.0 on end
 399 #                         device pci 00.0 on end
 400 #                         device pci 00.1 on end
 401 #                         device pci 00.2 on end
 402 #                         device pci 00.3 on end
 403 #                         device pci 00.4 on end
 404 #                        device pci 00.5 on end
 405 #               end
 406 #       end #pci_domain
 407
 408 #         chip drivers/generic/debug
 409 #                device pnp 0.0 off end # chip name
 410 #                 device pnp 0.1 on end # pci_regs_all
 411 #                 device pnp 0.2 off end # mem
 412 #                 device pnp 0.3 off end # cpuid
 413 #                 device pnp 0.4 off end # smbus_regs_all
 414 #                 device pnp 0.5 off end # dual core msr
 415 #                 device pnp 0.6 off end # cache size
 416 #                 device pnp 0.7 off end # tsc
 417 #                 device pnp 0.8 off end # hard reset
 418 #                 device pnp 0.9 off end # mcp55
 419 #                 device pnp 0.a on end # GH ext table
 420 #        end
 421
 422 end
 423
 424