src/mainboard/amd/serengeti_cheetah/romstage.c

   1 #if CONFIG_K8_REV_F_SUPPORT == 1
   2 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
   3 #endif
   4
   5 #include <stdint.h>
   6 #include <string.h>
   7 #include <device/pci_def.h>
   8 #include <device/pci_ids.h>
   9 #include <arch/io.h>
  10 #include <device/pnp_def.h>
  11 #include <arch/romcc_io.h>
  12 #include <cpu/x86/lapic.h>
  13 #include <pc80/mc146818rtc.h>
  14 #include <console/console.h>
  15 #include <cpu/amd/model_fxx_rev.h>
  16 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  17 #include <reset.h>
  18 #include "northbridge/amd/amdk8/raminit.h"
  19 #include "cpu/amd/model_fxx/apic_timer.c"
  20 #include "cpu/x86/lapic/boot_cpu.c"
  21 #include "northbridge/amd/amdk8/reset_test.c"
  22 #include "cpu/x86/bist.h"
  23 #include "lib/delay.c"
  24 #include "northbridge/amd/amdk8/debug.c"
  25 #include "cpu/x86/mtrr/earlymtrr.c"
  26 #include <cpu/amd/mtrr.h>
  27 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  28 #include "northbridge/amd/amdk8/setup_resource_map.c"
  29 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  30
  31 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  32
  33 static void memreset_setup(void)
  34 {
  35         //GPIO on amd8111 to enable MEMRST ????
  36         outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  37         outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  38 }
  39
  40 static void memreset(int controllers, const struct mem_controller *ctrl) { }
  41
  42 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  43 {
  44 #define SMBUS_HUB 0x18
  45         int ret,i;
  46         unsigned device=(ctrl->channel0[0])>>8;
  47         /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
  48         i=2;
  49         do {
  50                 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
  51         } while ((ret!=0) && (i-->0));
  52
  53         smbus_write_byte(SMBUS_HUB, 0x03, 0);
  54 }
  55
  56 #if 0
  57 static inline void change_i2c_mux(unsigned device)
  58 {
  59 #define SMBUS_HUB 0x18
  60         int ret, i;
  61         print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
  62         i=2;
  63         do {
  64                 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
  65                 print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n");
  66         } while ((ret!=0) && (i-->0));
  67         ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
  68         print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n");
  69 }
  70 #endif
  71
  72 static inline int spd_read_byte(unsigned device, unsigned address)
  73 {
  74         return smbus_read_byte(device, address);
  75 }
  76
  77 #include "northbridge/amd/amdk8/amdk8.h"
  78 #include "northbridge/amd/amdk8/incoherent_ht.c"
  79 #include "northbridge/amd/amdk8/coherent_ht.c"
  80 #include "northbridge/amd/amdk8/raminit_f.c"
  81 #include "lib/generic_sdram.c"
  82 #include "resourcemap.c"
  83 #include "cpu/amd/dualcore/dualcore.c"
  84 #include <spd.h>
  85 #include "cpu/amd/car/post_cache_as_ram.c"
  86 #include "cpu/amd/model_fxx/init_cpus.c"
  87 #include "cpu/amd/model_fxx/fidvid.c"
  88 #include "northbridge/amd/amdk8/early_ht.c"
  89
  90 #define RC0 ((1<<0)<<8)
  91 #define RC1 ((1<<1)<<8)
  92 #define RC2 ((1<<2)<<8)
  93 #define RC3 ((1<<3)<<8)
  94
  95 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  96 {
  97         static const uint16_t spd_addr[] = {
  98                         //first node
  99                         RC0|DIMM0, RC0|DIMM2, 0, 0,
 100                         RC0|DIMM1, RC0|DIMM3, 0, 0,
 101 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 102                         //second node
 103                         RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6,
 104                         RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7,
 105 #endif
 106 #if CONFIG_MAX_PHYSICAL_CPUS > 2
 107                         // third node
 108                         RC2|DIMM0, RC2|DIMM2, 0, 0,
 109                         RC2|DIMM1, RC2|DIMM3, 0, 0,
 110                         // four node
 111                         RC3|DIMM0, RC3|DIMM2, RC3|DIMM4, RC3|DIMM6,
 112                         RC3|DIMM1, RC3|DIMM3, RC3|DIMM5, RC3|DIMM7,
 113 #endif
 114
 115         };
 116
 117         struct sys_info *sysinfo = (void*)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 118         int needs_reset;
 119         unsigned bsp_apicid = 0;
 120 #if CONFIG_SET_FIDVID
 121         struct cpuid_result cpuid1;
 122 #endif
 123
 124         if (!cpu_init_detectedx && boot_cpu()) {
 125                 /* Nothing special needs to be done to find bus 0 */
 126                 /* Allow the HT devices to be found */
 127                 enumerate_ht_chain();
 128         }
 129
 130         if (bist == 0)
 131                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 132
 133         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 134         uart_init();
 135         console_init();
 136
 137 //      dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 138
 139         /* Halt if there was a built in self test failure */
 140         report_bist_failure(bist);
 141
 142         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 143
 144         setup_mb_resource_map();
 145 #if 0
 146         dump_pci_device(PCI_DEV(0, 0x18, 0));
 147         dump_pci_device(PCI_DEV(0, 0x19, 0));
 148 #endif
 149
 150         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 151
 152 #if CONFIG_MEM_TRAIN_SEQ == 1
 153         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 154 #endif
 155         setup_coherent_ht_domain(); // routing table and start other core0
 156
 157         wait_all_core0_started();
 158 #if CONFIG_LOGICAL_CPUS==1
 159         // It is said that we should start core1 after all core0 launched
 160         /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 161          * So here need to make sure last core0 is started, esp for two way system,
 162          * (there may be apic id conflicts in that case)
 163          */
 164         start_other_cores();
 165         wait_all_other_cores_started(bsp_apicid);
 166 #endif
 167
 168         /* it will set up chains and store link pair for optimization later */
 169         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 170
 171 #if 0
 172         //it your CPU min fid is 1G, you can change HT to 1G and FID to max one time.
 173         needs_reset = optimize_link_coherent_ht();
 174         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 175 #endif
 176
 177 #if CONFIG_SET_FIDVID
 178         /* Check to see if processor is capable of changing FIDVID  */
 179         /* otherwise it will throw a GP# when reading FIDVID_STATUS */
 180         cpuid1 = cpuid(0x80000007);
 181         if ((cpuid1.edx & 0x6) == 0x6) {
 182
 183         {
 184                 /* Read FIDVID_STATUS */
 185                 msr_t msr;
 186                 msr=rdmsr(0xc0010042);
 187                 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 188         }
 189
 190         enable_fid_change();
 191         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 192         init_fidvid_bsp(bsp_apicid);
 193
 194         // show final fid and vid
 195         {
 196                 msr_t msr;
 197                 msr=rdmsr(0xc0010042);
 198                 print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 199         }
 200
 201         } else {
 202                 print_debug("Changing FIDVID not supported\n");
 203         }
 204 #endif
 205
 206 #if 1
 207         needs_reset = optimize_link_coherent_ht();
 208         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 209
 210         // fidvid change will issue one LDTSTOP and the HT change will be effective too
 211         if (needs_reset) {
 212                 print_info("ht reset -\n");
 213                 soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
 214         }
 215 #endif
 216         allow_all_aps_stop(bsp_apicid);
 217
 218         //It's the time to set ctrl in sysinfo now;
 219         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 220
 221         enable_smbus();
 222
 223 #if 0
 224         int i;
 225         for(i=0;i<4;i++) {
 226                 activate_spd_rom(&cpu[i]);
 227                 dump_smbus_registers();
 228         }
 229 #endif
 230
 231 #if 0
 232         for(i=1;i<256;i<<=1) {
 233                 change_i2c_mux(i);
 234                 dump_smbus_registers();
 235         }
 236 #endif
 237
 238         memreset_setup();
 239
 240         //do we need apci timer, tsc...., only debug need it for better output
 241         /* all ap stopped? */
 242 //        init_timer(); // Need to use TMICT to synconize FID/VID
 243
 244         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 245
 246 #if 0
 247         print_pci_devices();
 248 #endif
 249
 250 #if 0
 251 //        dump_pci_devices();
 252         dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98);
 253         dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98);
 254 #endif
 255
 256         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
 257 }