src/mainboard/amd/serengeti_cheetah/romstage.c

   1 #if CONFIG_K8_REV_F_SUPPORT == 1
   2 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
   3 #endif
   4
   5 #include <stdint.h>
   6 #include <string.h>
   7 #include <device/pci_def.h>
   8 #include <device/pci_ids.h>
   9 #include <arch/io.h>
  10 #include <device/pnp_def.h>
  11 #include <arch/romcc_io.h>
  12 #include <cpu/x86/lapic.h>
  13 #include <pc80/mc146818rtc.h>
  14 #include <console/console.h>
  15 #include <cpu/amd/model_fxx_rev.h>
  16 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  17 #include <reset.h>
  18 #include "northbridge/amd/amdk8/raminit.h"
  19 #include "cpu/amd/model_fxx/apic_timer.c"
  20 #include "cpu/x86/lapic/boot_cpu.c"
  21 #include "northbridge/amd/amdk8/reset_test.c"
  22 #include "cpu/x86/bist.h"
  23 #include "lib/delay.c"
  24 #include "northbridge/amd/amdk8/debug.c"
  25 #include "cpu/x86/mtrr/earlymtrr.c"
  26 #include <cpu/amd/mtrr.h>
  27 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  28 #include "northbridge/amd/amdk8/setup_resource_map.c"
  29 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  30
  31 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  32
  33 static void memreset_setup(void)
  34 {
  35         //GPIO on amd8111 to enable MEMRST ????
  36         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  37         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  38 }
  39
  40 static void memreset(int controllers, const struct mem_controller *ctrl)
  41 {
  42 }
  43
  44 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  45 {
  46 #define SMBUS_HUB 0x18
  47         int ret,i;
  48         unsigned device=(ctrl->channel0[0])>>8;
  49         /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
  50         i=2;
  51         do {
  52                 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
  53         } while ((ret!=0) && (i-->0));
  54
  55         smbus_write_byte(SMBUS_HUB, 0x03, 0);
  56 }
  57 #if 0
  58 static inline void change_i2c_mux(unsigned device)
  59 {
  60 #define SMBUS_HUB 0x18
  61         int ret, i;
  62         print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
  63         i=2;
  64         do {
  65                 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
  66                 print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n");
  67         } while ((ret!=0) && (i-->0));
  68         ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
  69         print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n");
  70 }
  71 #endif
  72
  73 static inline int spd_read_byte(unsigned device, unsigned address)
  74 {
  75         return smbus_read_byte(device, address);
  76 }
  77
  78 #include "northbridge/amd/amdk8/amdk8.h"
  79 #include "northbridge/amd/amdk8/incoherent_ht.c"
  80 #include "northbridge/amd/amdk8/coherent_ht.c"
  81 #include "northbridge/amd/amdk8/raminit_f.c"
  82 #include "lib/generic_sdram.c"
  83 #include "resourcemap.c" /* tyan does not want the default */
  84 #include "cpu/amd/dualcore/dualcore.c"
  85 #include <spd.h>
  86 #include "cpu/amd/car/post_cache_as_ram.c"
  87 #include "cpu/amd/model_fxx/init_cpus.c"
  88 #include "cpu/amd/model_fxx/fidvid.c"
  89 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
  90 #include "northbridge/amd/amdk8/early_ht.c"
  91
  92 #define RC0 ((1<<0)<<8)
  93 #define RC1 ((1<<1)<<8)
  94 #define RC2 ((1<<2)<<8)
  95 #define RC3 ((1<<3)<<8)
  96
  97 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  98 {
  99         static const uint16_t spd_addr[] = {
 100                         //first node
 101                         RC0|DIMM0, RC0|DIMM2, 0, 0,
 102                         RC0|DIMM1, RC0|DIMM3, 0, 0,
 103 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 104                         //second node
 105                         RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6,
 106                         RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7,
 107 #endif
 108 #if CONFIG_MAX_PHYSICAL_CPUS > 2
 109                         // third node
 110                         RC2|DIMM0, RC2|DIMM2, 0, 0,
 111                         RC2|DIMM1, RC2|DIMM3, 0, 0,
 112                         // four node
 113                         RC3|DIMM0, RC3|DIMM2, RC3|DIMM4, RC3|DIMM6,
 114                         RC3|DIMM1, RC3|DIMM3, RC3|DIMM5, RC3|DIMM7,
 115 #endif
 116
 117         };
 118
 119         struct sys_info *sysinfo = (void*)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 120
 121         int needs_reset;
 122         unsigned bsp_apicid = 0;
 123 #if CONFIG_SET_FIDVID
 124         struct cpuid_result cpuid1;
 125 #endif
 126
 127         if (!cpu_init_detectedx && boot_cpu()) {
 128                 /* Nothing special needs to be done to find bus 0 */
 129                 /* Allow the HT devices to be found */
 130
 131                 enumerate_ht_chain();
 132
 133                 /* Setup the rom access for 4M */
 134                 amd8111_enable_rom();
 135         }
 136
 137         if (bist == 0) {
 138                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 139         }
 140
 141 //      post_code(0x32);
 142
 143         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 144         uart_init();
 145         console_init();
 146
 147 //      dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 148
 149         /* Halt if there was a built in self test failure */
 150         report_bist_failure(bist);
 151
 152         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 153
 154         setup_mb_resource_map();
 155 #if 0
 156         dump_pci_device(PCI_DEV(0, 0x18, 0));
 157         dump_pci_device(PCI_DEV(0, 0x19, 0));
 158 #endif
 159
 160         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 161
 162 #if CONFIG_MEM_TRAIN_SEQ == 1
 163         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 164 #endif
 165         setup_coherent_ht_domain(); // routing table and start other core0
 166
 167         wait_all_core0_started();
 168 #if CONFIG_LOGICAL_CPUS==1
 169         // It is said that we should start core1 after all core0 launched
 170         /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 171          * So here need to make sure last core0 is started, esp for two way system,
 172          * (there may be apic id conflicts in that case)
 173          */
 174         start_other_cores();
 175         wait_all_other_cores_started(bsp_apicid);
 176 #endif
 177
 178         /* it will set up chains and store link pair for optimization later */
 179         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 180
 181 #if 0
 182         //it your CPU min fid is 1G, you can change HT to 1G and FID to max one time.
 183         needs_reset = optimize_link_coherent_ht();
 184         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 185 #endif
 186
 187 #if CONFIG_SET_FIDVID
 188         /* Check to see if processor is capable of changing FIDVID  */
 189         /* otherwise it will throw a GP# when reading FIDVID_STATUS */
 190         cpuid1 = cpuid(0x80000007);
 191         if( (cpuid1.edx & 0x6) == 0x6 ) {
 192
 193         {
 194                 /* Read FIDVID_STATUS */
 195                 msr_t msr;
 196                 msr=rdmsr(0xc0010042);
 197                 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 198
 199         }
 200
 201         enable_fid_change();
 202
 203         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 204
 205         init_fidvid_bsp(bsp_apicid);
 206
 207         // show final fid and vid
 208         {
 209                 msr_t msr;
 210                 msr=rdmsr(0xc0010042);
 211                 print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 212
 213         }
 214
 215         } else {
 216                 print_debug("Changing FIDVID not supported\n");
 217         }
 218
 219 #endif
 220
 221 #if 1
 222         needs_reset = optimize_link_coherent_ht();
 223         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 224
 225         // fidvid change will issue one LDTSTOP and the HT change will be effective too
 226         if (needs_reset) {
 227                 print_info("ht reset -\n");
 228                 soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
 229         }
 230 #endif
 231         allow_all_aps_stop(bsp_apicid);
 232
 233         //It's the time to set ctrl in sysinfo now;
 234         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 235
 236         enable_smbus();
 237
 238 #if 0
 239         int i;
 240         for(i=0;i<4;i++) {
 241                 activate_spd_rom(&cpu[i]);
 242                 dump_smbus_registers();
 243         }
 244 #endif
 245
 246 #if 0
 247         for(i=1;i<256;i<<=1) {
 248                 change_i2c_mux(i);
 249                 dump_smbus_registers();
 250         }
 251 #endif
 252
 253         memreset_setup();
 254
 255         //do we need apci timer, tsc...., only debug need it for better output
 256         /* all ap stopped? */
 257 //        init_timer(); // Need to use TMICT to synconize FID/VID
 258
 259         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 260
 261 #if 0
 262         print_pci_devices();
 263 #endif
 264
 265 #if 0
 266 //        dump_pci_devices();
 267         dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98);
 268         dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98);
 269 #endif
 270
 271         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
 272 }