src/mainboard/amd/serengeti_cheetah/romstage.c

   1 #define SET_NB_CFG_54 1
   2
   3 //used by raminit
   4
   5 //used by incoherent_ht
   6 //#define K8_ALLOCATE_IO_RANGE 1
   7
   8 //used by init_cpus and fidvid
   9 #define SET_FIDVID 0
  10 //if we want to wait for core1 done before DQS training, set it to 0
  11 #define SET_FIDVID_CORE0_ONLY 1
  12
  13 #if CONFIG_K8_REV_F_SUPPORT == 1
  14 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
  15 #endif
  16
  17 #include <stdint.h>
  18 #include <string.h>
  19 #include <device/pci_def.h>
  20 #include <device/pci_ids.h>
  21 #include <arch/io.h>
  22 #include <device/pnp_def.h>
  23 #include <arch/romcc_io.h>
  24 #include <cpu/x86/lapic.h>
  25 #include <pc80/mc146818rtc.h>
  26
  27 #include <console/console.h>
  28 #include <cpu/amd/model_fxx_rev.h>
  29 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  30 #include <reset.h>
  31 #include "northbridge/amd/amdk8/raminit.h"
  32 #include "cpu/amd/model_fxx/apic_timer.c"
  33
  34 #include "cpu/x86/lapic/boot_cpu.c"
  35 #include "northbridge/amd/amdk8/reset_test.c"
  36
  37 #include "cpu/x86/bist.h"
  38
  39 #include "lib/delay.c"
  40
  41 #include "northbridge/amd/amdk8/debug.c"
  42 #include "cpu/x86/mtrr/earlymtrr.c"
  43 #include <cpu/amd/mtrr.h>
  44 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  45
  46 #include "northbridge/amd/amdk8/setup_resource_map.c"
  47
  48 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  49
  50 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  51
  52 static void memreset_setup(void)
  53 {
  54         //GPIO on amd8111 to enable MEMRST ????
  55         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  56         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  57 }
  58
  59 static void memreset(int controllers, const struct mem_controller *ctrl)
  60 {
  61 }
  62
  63 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  64 {
  65 #define SMBUS_HUB 0x18
  66         int ret,i;
  67         unsigned device=(ctrl->channel0[0])>>8;
  68         /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
  69         i=2;
  70         do {
  71                 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
  72         } while ((ret!=0) && (i-->0));
  73
  74         smbus_write_byte(SMBUS_HUB, 0x03, 0);
  75 }
  76 #if 0
  77 static inline void change_i2c_mux(unsigned device)
  78 {
  79 #define SMBUS_HUB 0x18
  80         int ret, i;
  81         print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
  82         i=2;
  83         do {
  84                 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
  85                 print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n");
  86         } while ((ret!=0) && (i-->0));
  87         ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
  88         print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n");
  89 }
  90 #endif
  91
  92 static inline int spd_read_byte(unsigned device, unsigned address)
  93 {
  94         return smbus_read_byte(device, address);
  95 }
  96
  97 #include "northbridge/amd/amdk8/amdk8.h"
  98 #include "northbridge/amd/amdk8/incoherent_ht.c"
  99 #include "northbridge/amd/amdk8/coherent_ht.c"
 100 #include "northbridge/amd/amdk8/raminit_f.c"
 101 #include "lib/generic_sdram.c"
 102
 103  /* tyan does not want the default */
 104 #include "resourcemap.c"
 105
 106 #include "cpu/amd/dualcore/dualcore.c"
 107
 108 #define RC0 ((1<<0)<<8)
 109 #define RC1 ((1<<1)<<8)
 110 #define RC2 ((1<<2)<<8)
 111 #define RC3 ((1<<3)<<8)
 112
 113 #define DIMM0 0x50
 114 #define DIMM1 0x51
 115 #define DIMM2 0x52
 116 #define DIMM3 0x53
 117 #define DIMM4 0x54
 118 #define DIMM5 0x55
 119 #define DIMM6 0x56
 120 #define DIMM7 0x57
 121
 122
 123 #include "cpu/amd/car/post_cache_as_ram.c"
 124
 125 #include "cpu/amd/model_fxx/init_cpus.c"
 126
 127 #include "cpu/amd/model_fxx/fidvid.c"
 128
 129 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 130 #include "northbridge/amd/amdk8/early_ht.c"
 131
 132 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 133 {
 134         static const uint16_t spd_addr[] = {
 135                         //first node
 136                         RC0|DIMM0, RC0|DIMM2, 0, 0,
 137                         RC0|DIMM1, RC0|DIMM3, 0, 0,
 138 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 139                         //second node
 140                         RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6,
 141                         RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7,
 142 #endif
 143 #if CONFIG_MAX_PHYSICAL_CPUS > 2
 144                         // third node
 145                         RC2|DIMM0, RC2|DIMM2, 0, 0,
 146                         RC2|DIMM1, RC2|DIMM3, 0, 0,
 147                         // four node
 148                         RC3|DIMM0, RC3|DIMM2, RC3|DIMM4, RC3|DIMM6,
 149                         RC3|DIMM1, RC3|DIMM3, RC3|DIMM5, RC3|DIMM7,
 150 #endif
 151
 152         };
 153
 154         struct sys_info *sysinfo = (void*)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 155
 156         int needs_reset;
 157         unsigned bsp_apicid = 0;
 158 #if SET_FIDVID == 1
 159         struct cpuid_result cpuid1;
 160 #endif
 161
 162         if (!cpu_init_detectedx && boot_cpu()) {
 163                 /* Nothing special needs to be done to find bus 0 */
 164                 /* Allow the HT devices to be found */
 165
 166                 enumerate_ht_chain();
 167
 168                 /* Setup the rom access for 4M */
 169                 amd8111_enable_rom();
 170         }
 171
 172         if (bist == 0) {
 173                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 174         }
 175
 176 //      post_code(0x32);
 177
 178         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 179         uart_init();
 180         console_init();
 181
 182 //      dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 183
 184         /* Halt if there was a built in self test failure */
 185         report_bist_failure(bist);
 186
 187         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 188
 189         setup_mb_resource_map();
 190 #if 0
 191         dump_pci_device(PCI_DEV(0, 0x18, 0));
 192         dump_pci_device(PCI_DEV(0, 0x19, 0));
 193 #endif
 194
 195         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 196
 197 #if CONFIG_MEM_TRAIN_SEQ == 1
 198         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 199 #endif
 200         setup_coherent_ht_domain(); // routing table and start other core0
 201
 202         wait_all_core0_started();
 203 #if CONFIG_LOGICAL_CPUS==1
 204         // It is said that we should start core1 after all core0 launched
 205         /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 206          * So here need to make sure last core0 is started, esp for two way system,
 207          * (there may be apic id conflicts in that case)
 208          */
 209         start_other_cores();
 210         wait_all_other_cores_started(bsp_apicid);
 211 #endif
 212
 213         /* it will set up chains and store link pair for optimization later */
 214         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 215
 216 #if 0
 217         //it your CPU min fid is 1G, you can change HT to 1G and FID to max one time.
 218         needs_reset = optimize_link_coherent_ht();
 219         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 220 #endif
 221
 222 #if SET_FIDVID == 1
 223         /* Check to see if processor is capable of changing FIDVID  */
 224         /* otherwise it will throw a GP# when reading FIDVID_STATUS */
 225         cpuid1 = cpuid(0x80000007);
 226         if( (cpuid1.edx & 0x6) == 0x6 ) {
 227
 228         {
 229                 /* Read FIDVID_STATUS */
 230                 msr_t msr;
 231                 msr=rdmsr(0xc0010042);
 232                 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 233
 234         }
 235
 236         enable_fid_change();
 237
 238         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 239
 240         init_fidvid_bsp(bsp_apicid);
 241
 242         // show final fid and vid
 243         {
 244                 msr_t msr;
 245                 msr=rdmsr(0xc0010042);
 246                 print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 247
 248         }
 249
 250         } else {
 251                 print_debug("Changing FIDVID not supported\n");
 252         }
 253
 254 #endif
 255
 256 #if 1
 257         needs_reset = optimize_link_coherent_ht();
 258         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 259
 260         // fidvid change will issue one LDTSTOP and the HT change will be effective too
 261         if (needs_reset) {
 262                 print_info("ht reset -\n");
 263                 soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
 264         }
 265 #endif
 266         allow_all_aps_stop(bsp_apicid);
 267
 268         //It's the time to set ctrl in sysinfo now;
 269         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 270
 271         enable_smbus();
 272
 273 #if 0
 274         int i;
 275         for(i=0;i<4;i++) {
 276                 activate_spd_rom(&cpu[i]);
 277                 dump_smbus_registers();
 278         }
 279 #endif
 280
 281 #if 0
 282         for(i=1;i<256;i<<=1) {
 283                 change_i2c_mux(i);
 284                 dump_smbus_registers();
 285         }
 286 #endif
 287
 288         memreset_setup();
 289
 290         //do we need apci timer, tsc...., only debug need it for better output
 291         /* all ap stopped? */
 292 //        init_timer(); // Need to use TMICT to synconize FID/VID
 293
 294         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 295
 296 #if 0
 297         print_pci_devices();
 298 #endif
 299
 300 #if 0
 301 //        dump_pci_devices();
 302         dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98);
 303         dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98);
 304 #endif
 305
 306         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
 307
 308 }
 309