src/mainboard/amd/serengeti_cheetah/romstage.c

   1 #if CONFIG_K8_REV_F_SUPPORT == 1
   2 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
   3 #endif
   4
   5 #include <stdint.h>
   6 #include <string.h>
   7 #include <device/pci_def.h>
   8 #include <device/pci_ids.h>
   9 #include <arch/io.h>
  10 #include <device/pnp_def.h>
  11 #include <arch/romcc_io.h>
  12 #include <cpu/x86/lapic.h>
  13 #include <pc80/mc146818rtc.h>
  14
  15 #include <console/console.h>
  16 #include <cpu/amd/model_fxx_rev.h>
  17 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  18 #include <reset.h>
  19 #include "northbridge/amd/amdk8/raminit.h"
  20 #include "cpu/amd/model_fxx/apic_timer.c"
  21
  22 #include "cpu/x86/lapic/boot_cpu.c"
  23 #include "northbridge/amd/amdk8/reset_test.c"
  24
  25 #include "cpu/x86/bist.h"
  26
  27 #include "lib/delay.c"
  28
  29 #include "northbridge/amd/amdk8/debug.c"
  30 #include "cpu/x86/mtrr/earlymtrr.c"
  31 #include <cpu/amd/mtrr.h>
  32 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  33
  34 #include "northbridge/amd/amdk8/setup_resource_map.c"
  35
  36 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  37
  38 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  39
  40 static void memreset_setup(void)
  41 {
  42         //GPIO on amd8111 to enable MEMRST ????
  43         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  44         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  45 }
  46
  47 static void memreset(int controllers, const struct mem_controller *ctrl)
  48 {
  49 }
  50
  51 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  52 {
  53 #define SMBUS_HUB 0x18
  54         int ret,i;
  55         unsigned device=(ctrl->channel0[0])>>8;
  56         /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
  57         i=2;
  58         do {
  59                 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
  60         } while ((ret!=0) && (i-->0));
  61
  62         smbus_write_byte(SMBUS_HUB, 0x03, 0);
  63 }
  64 #if 0
  65 static inline void change_i2c_mux(unsigned device)
  66 {
  67 #define SMBUS_HUB 0x18
  68         int ret, i;
  69         print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
  70         i=2;
  71         do {
  72                 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
  73                 print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n");
  74         } while ((ret!=0) && (i-->0));
  75         ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
  76         print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n");
  77 }
  78 #endif
  79
  80 static inline int spd_read_byte(unsigned device, unsigned address)
  81 {
  82         return smbus_read_byte(device, address);
  83 }
  84
  85 #include "northbridge/amd/amdk8/amdk8.h"
  86 #include "northbridge/amd/amdk8/incoherent_ht.c"
  87 #include "northbridge/amd/amdk8/coherent_ht.c"
  88 #include "northbridge/amd/amdk8/raminit_f.c"
  89 #include "lib/generic_sdram.c"
  90
  91  /* tyan does not want the default */
  92 #include "resourcemap.c"
  93
  94 #include "cpu/amd/dualcore/dualcore.c"
  95 #include <spd.h>
  96
  97 #define RC0 ((1<<0)<<8)
  98 #define RC1 ((1<<1)<<8)
  99 #define RC2 ((1<<2)<<8)
 100 #define RC3 ((1<<3)<<8)
 101
 102 #include "cpu/amd/car/post_cache_as_ram.c"
 103
 104 #include "cpu/amd/model_fxx/init_cpus.c"
 105
 106 #include "cpu/amd/model_fxx/fidvid.c"
 107
 108 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 109 #include "northbridge/amd/amdk8/early_ht.c"
 110
 111 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 112 {
 113         static const uint16_t spd_addr[] = {
 114                         //first node
 115                         RC0|DIMM0, RC0|DIMM2, 0, 0,
 116                         RC0|DIMM1, RC0|DIMM3, 0, 0,
 117 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 118                         //second node
 119                         RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6,
 120                         RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7,
 121 #endif
 122 #if CONFIG_MAX_PHYSICAL_CPUS > 2
 123                         // third node
 124                         RC2|DIMM0, RC2|DIMM2, 0, 0,
 125                         RC2|DIMM1, RC2|DIMM3, 0, 0,
 126                         // four node
 127                         RC3|DIMM0, RC3|DIMM2, RC3|DIMM4, RC3|DIMM6,
 128                         RC3|DIMM1, RC3|DIMM3, RC3|DIMM5, RC3|DIMM7,
 129 #endif
 130
 131         };
 132
 133         struct sys_info *sysinfo = (void*)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 134
 135         int needs_reset;
 136         unsigned bsp_apicid = 0;
 137 #if CONFIG_SET_FIDVID
 138         struct cpuid_result cpuid1;
 139 #endif
 140
 141         if (!cpu_init_detectedx && boot_cpu()) {
 142                 /* Nothing special needs to be done to find bus 0 */
 143                 /* Allow the HT devices to be found */
 144
 145                 enumerate_ht_chain();
 146
 147                 /* Setup the rom access for 4M */
 148                 amd8111_enable_rom();
 149         }
 150
 151         if (bist == 0) {
 152                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 153         }
 154
 155 //      post_code(0x32);
 156
 157         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 158         uart_init();
 159         console_init();
 160
 161 //      dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 162
 163         /* Halt if there was a built in self test failure */
 164         report_bist_failure(bist);
 165
 166         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 167
 168         setup_mb_resource_map();
 169 #if 0
 170         dump_pci_device(PCI_DEV(0, 0x18, 0));
 171         dump_pci_device(PCI_DEV(0, 0x19, 0));
 172 #endif
 173
 174         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 175
 176 #if CONFIG_MEM_TRAIN_SEQ == 1
 177         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 178 #endif
 179         setup_coherent_ht_domain(); // routing table and start other core0
 180
 181         wait_all_core0_started();
 182 #if CONFIG_LOGICAL_CPUS==1
 183         // It is said that we should start core1 after all core0 launched
 184         /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 185          * So here need to make sure last core0 is started, esp for two way system,
 186          * (there may be apic id conflicts in that case)
 187          */
 188         start_other_cores();
 189         wait_all_other_cores_started(bsp_apicid);
 190 #endif
 191
 192         /* it will set up chains and store link pair for optimization later */
 193         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 194
 195 #if 0
 196         //it your CPU min fid is 1G, you can change HT to 1G and FID to max one time.
 197         needs_reset = optimize_link_coherent_ht();
 198         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 199 #endif
 200
 201 #if CONFIG_SET_FIDVID
 202         /* Check to see if processor is capable of changing FIDVID  */
 203         /* otherwise it will throw a GP# when reading FIDVID_STATUS */
 204         cpuid1 = cpuid(0x80000007);
 205         if( (cpuid1.edx & 0x6) == 0x6 ) {
 206
 207         {
 208                 /* Read FIDVID_STATUS */
 209                 msr_t msr;
 210                 msr=rdmsr(0xc0010042);
 211                 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 212
 213         }
 214
 215         enable_fid_change();
 216
 217         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 218
 219         init_fidvid_bsp(bsp_apicid);
 220
 221         // show final fid and vid
 222         {
 223                 msr_t msr;
 224                 msr=rdmsr(0xc0010042);
 225                 print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 226
 227         }
 228
 229         } else {
 230                 print_debug("Changing FIDVID not supported\n");
 231         }
 232
 233 #endif
 234
 235 #if 1
 236         needs_reset = optimize_link_coherent_ht();
 237         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 238
 239         // fidvid change will issue one LDTSTOP and the HT change will be effective too
 240         if (needs_reset) {
 241                 print_info("ht reset -\n");
 242                 soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
 243         }
 244 #endif
 245         allow_all_aps_stop(bsp_apicid);
 246
 247         //It's the time to set ctrl in sysinfo now;
 248         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 249
 250         enable_smbus();
 251
 252 #if 0
 253         int i;
 254         for(i=0;i<4;i++) {
 255                 activate_spd_rom(&cpu[i]);
 256                 dump_smbus_registers();
 257         }
 258 #endif
 259
 260 #if 0
 261         for(i=1;i<256;i<<=1) {
 262                 change_i2c_mux(i);
 263                 dump_smbus_registers();
 264         }
 265 #endif
 266
 267         memreset_setup();
 268
 269         //do we need apci timer, tsc...., only debug need it for better output
 270         /* all ap stopped? */
 271 //        init_timer(); // Need to use TMICT to synconize FID/VID
 272
 273         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 274
 275 #if 0
 276         print_pci_devices();
 277 #endif
 278
 279 #if 0
 280 //        dump_pci_devices();
 281         dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98);
 282         dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98);
 283 #endif
 284
 285         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
 286
 287 }
 288