src/mainboard/amd/serengeti_cheetah/romstage.c

   1 #define SET_NB_CFG_54 1
   2
   3 //used by incoherent_ht
   4 //#define K8_ALLOCATE_IO_RANGE 1
   5
   6 //used by init_cpus and fidvid
   7 #define SET_FIDVID 0
   8 //if we want to wait for core1 done before DQS training, set it to 0
   9 #define SET_FIDVID_CORE0_ONLY 1
  10
  11 #if CONFIG_K8_REV_F_SUPPORT == 1
  12 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
  13 #endif
  14
  15 #include <stdint.h>
  16 #include <string.h>
  17 #include <device/pci_def.h>
  18 #include <device/pci_ids.h>
  19 #include <arch/io.h>
  20 #include <device/pnp_def.h>
  21 #include <arch/romcc_io.h>
  22 #include <cpu/x86/lapic.h>
  23 #include <pc80/mc146818rtc.h>
  24
  25 #include <console/console.h>
  26 #include <cpu/amd/model_fxx_rev.h>
  27 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  28 #include <reset.h>
  29 #include "northbridge/amd/amdk8/raminit.h"
  30 #include "cpu/amd/model_fxx/apic_timer.c"
  31
  32 #include "cpu/x86/lapic/boot_cpu.c"
  33 #include "northbridge/amd/amdk8/reset_test.c"
  34
  35 #include "cpu/x86/bist.h"
  36
  37 #include "lib/delay.c"
  38
  39 #include "northbridge/amd/amdk8/debug.c"
  40 #include "cpu/x86/mtrr/earlymtrr.c"
  41 #include <cpu/amd/mtrr.h>
  42 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  43
  44 #include "northbridge/amd/amdk8/setup_resource_map.c"
  45
  46 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  47
  48 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  49
  50 static void memreset_setup(void)
  51 {
  52         //GPIO on amd8111 to enable MEMRST ????
  53         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  54         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  55 }
  56
  57 static void memreset(int controllers, const struct mem_controller *ctrl)
  58 {
  59 }
  60
  61 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  62 {
  63 #define SMBUS_HUB 0x18
  64         int ret,i;
  65         unsigned device=(ctrl->channel0[0])>>8;
  66         /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
  67         i=2;
  68         do {
  69                 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
  70         } while ((ret!=0) && (i-->0));
  71
  72         smbus_write_byte(SMBUS_HUB, 0x03, 0);
  73 }
  74 #if 0
  75 static inline void change_i2c_mux(unsigned device)
  76 {
  77 #define SMBUS_HUB 0x18
  78         int ret, i;
  79         print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
  80         i=2;
  81         do {
  82                 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
  83                 print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n");
  84         } while ((ret!=0) && (i-->0));
  85         ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
  86         print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n");
  87 }
  88 #endif
  89
  90 static inline int spd_read_byte(unsigned device, unsigned address)
  91 {
  92         return smbus_read_byte(device, address);
  93 }
  94
  95 #include "northbridge/amd/amdk8/amdk8.h"
  96 #include "northbridge/amd/amdk8/incoherent_ht.c"
  97 #include "northbridge/amd/amdk8/coherent_ht.c"
  98 #include "northbridge/amd/amdk8/raminit_f.c"
  99 #include "lib/generic_sdram.c"
 100
 101  /* tyan does not want the default */
 102 #include "resourcemap.c"
 103
 104 #include "cpu/amd/dualcore/dualcore.c"
 105
 106 #define RC0 ((1<<0)<<8)
 107 #define RC1 ((1<<1)<<8)
 108 #define RC2 ((1<<2)<<8)
 109 #define RC3 ((1<<3)<<8)
 110
 111 #define DIMM0 0x50
 112 #define DIMM1 0x51
 113 #define DIMM2 0x52
 114 #define DIMM3 0x53
 115 #define DIMM4 0x54
 116 #define DIMM5 0x55
 117 #define DIMM6 0x56
 118 #define DIMM7 0x57
 119
 120
 121 #include "cpu/amd/car/post_cache_as_ram.c"
 122
 123 #include "cpu/amd/model_fxx/init_cpus.c"
 124
 125 #include "cpu/amd/model_fxx/fidvid.c"
 126
 127 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 128 #include "northbridge/amd/amdk8/early_ht.c"
 129
 130 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 131 {
 132         static const uint16_t spd_addr[] = {
 133                         //first node
 134                         RC0|DIMM0, RC0|DIMM2, 0, 0,
 135                         RC0|DIMM1, RC0|DIMM3, 0, 0,
 136 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 137                         //second node
 138                         RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6,
 139                         RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7,
 140 #endif
 141 #if CONFIG_MAX_PHYSICAL_CPUS > 2
 142                         // third node
 143                         RC2|DIMM0, RC2|DIMM2, 0, 0,
 144                         RC2|DIMM1, RC2|DIMM3, 0, 0,
 145                         // four node
 146                         RC3|DIMM0, RC3|DIMM2, RC3|DIMM4, RC3|DIMM6,
 147                         RC3|DIMM1, RC3|DIMM3, RC3|DIMM5, RC3|DIMM7,
 148 #endif
 149
 150         };
 151
 152         struct sys_info *sysinfo = (void*)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 153
 154         int needs_reset;
 155         unsigned bsp_apicid = 0;
 156 #if SET_FIDVID == 1
 157         struct cpuid_result cpuid1;
 158 #endif
 159
 160         if (!cpu_init_detectedx && boot_cpu()) {
 161                 /* Nothing special needs to be done to find bus 0 */
 162                 /* Allow the HT devices to be found */
 163
 164                 enumerate_ht_chain();
 165
 166                 /* Setup the rom access for 4M */
 167                 amd8111_enable_rom();
 168         }
 169
 170         if (bist == 0) {
 171                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 172         }
 173
 174 //      post_code(0x32);
 175
 176         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 177         uart_init();
 178         console_init();
 179
 180 //      dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 181
 182         /* Halt if there was a built in self test failure */
 183         report_bist_failure(bist);
 184
 185         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 186
 187         setup_mb_resource_map();
 188 #if 0
 189         dump_pci_device(PCI_DEV(0, 0x18, 0));
 190         dump_pci_device(PCI_DEV(0, 0x19, 0));
 191 #endif
 192
 193         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 194
 195 #if CONFIG_MEM_TRAIN_SEQ == 1
 196         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 197 #endif
 198         setup_coherent_ht_domain(); // routing table and start other core0
 199
 200         wait_all_core0_started();
 201 #if CONFIG_LOGICAL_CPUS==1
 202         // It is said that we should start core1 after all core0 launched
 203         /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 204          * So here need to make sure last core0 is started, esp for two way system,
 205          * (there may be apic id conflicts in that case)
 206          */
 207         start_other_cores();
 208         wait_all_other_cores_started(bsp_apicid);
 209 #endif
 210
 211         /* it will set up chains and store link pair for optimization later */
 212         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 213
 214 #if 0
 215         //it your CPU min fid is 1G, you can change HT to 1G and FID to max one time.
 216         needs_reset = optimize_link_coherent_ht();
 217         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 218 #endif
 219
 220 #if SET_FIDVID == 1
 221         /* Check to see if processor is capable of changing FIDVID  */
 222         /* otherwise it will throw a GP# when reading FIDVID_STATUS */
 223         cpuid1 = cpuid(0x80000007);
 224         if( (cpuid1.edx & 0x6) == 0x6 ) {
 225
 226         {
 227                 /* Read FIDVID_STATUS */
 228                 msr_t msr;
 229                 msr=rdmsr(0xc0010042);
 230                 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 231
 232         }
 233
 234         enable_fid_change();
 235
 236         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 237
 238         init_fidvid_bsp(bsp_apicid);
 239
 240         // show final fid and vid
 241         {
 242                 msr_t msr;
 243                 msr=rdmsr(0xc0010042);
 244                 print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 245
 246         }
 247
 248         } else {
 249                 print_debug("Changing FIDVID not supported\n");
 250         }
 251
 252 #endif
 253
 254 #if 1
 255         needs_reset = optimize_link_coherent_ht();
 256         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 257
 258         // fidvid change will issue one LDTSTOP and the HT change will be effective too
 259         if (needs_reset) {
 260                 print_info("ht reset -\n");
 261                 soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
 262         }
 263 #endif
 264         allow_all_aps_stop(bsp_apicid);
 265
 266         //It's the time to set ctrl in sysinfo now;
 267         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 268
 269         enable_smbus();
 270
 271 #if 0
 272         int i;
 273         for(i=0;i<4;i++) {
 274                 activate_spd_rom(&cpu[i]);
 275                 dump_smbus_registers();
 276         }
 277 #endif
 278
 279 #if 0
 280         for(i=1;i<256;i<<=1) {
 281                 change_i2c_mux(i);
 282                 dump_smbus_registers();
 283         }
 284 #endif
 285
 286         memreset_setup();
 287
 288         //do we need apci timer, tsc...., only debug need it for better output
 289         /* all ap stopped? */
 290 //        init_timer(); // Need to use TMICT to synconize FID/VID
 291
 292         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 293
 294 #if 0
 295         print_pci_devices();
 296 #endif
 297
 298 #if 0
 299 //        dump_pci_devices();
 300         dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98);
 301         dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98);
 302 #endif
 303
 304         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
 305
 306 }
 307