src/mainboard/amd/serengeti_cheetah/mptable.c

   1 #include <console/console.h>
   2 #include <arch/smp/mpspec.h>
   3 #include <arch/ioapic.h>
   4 #include <device/pci.h>
   5 #include <string.h>
   6 #include <stdint.h>
   7 #if CONFIG_LOGICAL_CPUS==1
   8 #include <cpu/amd/multicore.h>
   9 #endif
  10 #include <cpu/amd/amdk8_sysconf.h>
  11 #include "mb_sysconf.h"
  12
  13 static void *smp_write_config_table(void *v)
  14 {
  15         struct mp_config_table *mc;
  16         int i, j, bus_isa;
  17         struct mb_sysconf_t *m;
  18
  19         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
  20
  21         mptable_init(mc, LAPIC_ADDR);
  22
  23         smp_write_processors(mc);
  24
  25         get_bus_conf();
  26
  27         m = sysconf.mb;
  28
  29         mptable_write_buses(mc, NULL, &bus_isa);
  30
  31 /*I/O APICs:    APIC ID Version State           Address*/
  32         smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111
  33         {
  34                 device_t dev;
  35                 struct resource *res;
  36                 dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1));
  37                 if (dev) {
  38                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
  39                         if (res) {
  40                                 smp_write_ioapic(mc, m->apicid_8132_1, 0x11, res->base);
  41                         }
  42                 }
  43                 dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1));
  44                 if (dev) {
  45                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
  46                         if (res) {
  47                                 smp_write_ioapic(mc, m->apicid_8132_2, 0x11, res->base);
  48                         }
  49                 }
  50
  51                 j = 0;
  52
  53                 for(i=1; i< sysconf.hc_possible_num; i++) {
  54                         if(!(sysconf.pci1234[i] & 0x1) ) continue;
  55
  56                         switch(sysconf.hcid[i]) {
  57                         case 1: // 8132
  58                         case 3: // 8131
  59                                 dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
  60                                 if (dev) {
  61                                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
  62                                         if (res) {
  63                                                 smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11, res->base);
  64                                         }
  65                                 }
  66                                 dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
  67                                 if (dev) {
  68                                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
  69                                         if (res) {
  70                                                 smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11, res->base);
  71                                         }
  72                                 }
  73                                 break;
  74                         }
  75                         j++;
  76                 }
  77
  78         }
  79
  80         mptable_add_isa_interrupts(mc, bus_isa, m->apicid_8111, 0);
  81
  82 /*I/O Ints:     Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
  83 //??? What
  84         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13);
  85
  86 // Onboard AMD USB
  87         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0<<2)|3, m->apicid_8111, 0x13);
  88
  89 //Slot 3  PCI 32
  90         for(i=0;i<4;i++) {
  91                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5<<2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16
  92         }
  93
  94
  95 //Slot 4 PCI 32
  96         for(i=0;i<4;i++) {
  97                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4<<2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16
  98         }
  99
 100
 101 //Slot 1 PCI-X 133/100/66
 102         for(i=0;i<4;i++) {
 103                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1<<2)|i, m->apicid_8132_2, (0+i)%4); //
 104         }
 105
 106
 107 //Slot 2 PCI-X 133/100/66
 108         for(i=0;i<4;i++) {
 109                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1<<2)|i, m->apicid_8132_1, (1+i)%4); //25
 110         }
 111
 112         j = 0;
 113
 114         for(i=1; i< sysconf.hc_possible_num; i++) {
 115                 if(!(sysconf.pci1234[i] & 0x1) ) continue;
 116                 int ii;
 117                 device_t dev;
 118                 struct resource *res;
 119                 switch(sysconf.hcid[i]) {
 120                 case 1:
 121                 case 3:
 122                         dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
 123                         if (dev) {
 124                                 res = find_resource(dev, PCI_BASE_ADDRESS_0);
 125                                 if (res) {
 126                                         //Slot 1 PCI-X 133/100/66
 127                                         for(ii=0;ii<4;ii++) {
 128                                                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0<<2)|ii, m->apicid_8132a[j][0], (0+ii)%4); //
 129                                         }
 130                                 }
 131                         }
 132
 133                         dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
 134                         if (dev) {
 135                                 res = find_resource(dev, PCI_BASE_ADDRESS_0);
 136                                 if (res) {
 137                                         //Slot 2 PCI-X 133/100/66
 138                                         for(ii=0;ii<4;ii++) {
 139                                                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0<<2)|ii, m->apicid_8132a[j][1], (0+ii)%4); //25
 140                                         }
 141                                 }
 142                         }
 143
 144                         break;
 145                 case 2:
 146
 147                 //  Slot AGP
 148                         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151[j][1], 0x0, m->apicid_8111, 0x11);
 149                         break;
 150                 }
 151
 152                 j++;
 153         }
 154
 155
 156
 157 /*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN#*/
 158         mptable_lintsrc(mc, bus_isa);
 159         /* There is no extension information... */
 160
 161         /* Compute the checksums */
 162         return mptable_finalize(mc);
 163 }
 164
 165 unsigned long write_smp_table(unsigned long addr)
 166 {
 167         void *v;
 168         v = smp_write_floating_table(addr, 0);
 169         return (unsigned long)smp_write_config_table(v);
 170 }