src/mainboard/amd/serengeti_cheetah/mptable.c

   1 #include <console/console.h>
   2 #include <arch/smp/mpspec.h>
   3 #include <arch/ioapic.h>
   4 #include <device/pci.h>
   5 #include <string.h>
   6 #include <stdint.h>
   7 #if CONFIG_LOGICAL_CPUS==1
   8 #include <cpu/amd/multicore.h>
   9 #endif
  10
  11 #include <cpu/amd/amdk8_sysconf.h>
  12 #include "mb_sysconf.h"
  13
  14
  15
  16 static void *smp_write_config_table(void *v)
  17 {
  18         static const char sig[4] = "PCMP";
  19         static const char oem[8] = "COREBOOT";
  20         static const char productid[12] = "SERENGETI   ";
  21         struct mp_config_table *mc;
  22
  23         unsigned char bus_num;
  24         int i, j;
  25         struct mb_sysconf_t *m;
  26
  27         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
  28         memset(mc, 0, sizeof(*mc));
  29
  30         memcpy(mc->mpc_signature, sig, sizeof(sig));
  31         mc->mpc_length = sizeof(*mc); /* initially just the header */
  32         mc->mpc_spec = 0x04;
  33         mc->mpc_checksum = 0; /* not yet computed */
  34         memcpy(mc->mpc_oem, oem, sizeof(oem));
  35         memcpy(mc->mpc_productid, productid, sizeof(productid));
  36         mc->mpc_oemptr = 0;
  37         mc->mpc_oemsize = 0;
  38         mc->mpc_entry_count = 0; /* No entries yet... */
  39         mc->mpc_lapic = LAPIC_ADDR;
  40         mc->mpe_length = 0;
  41         mc->mpe_checksum = 0;
  42         mc->reserved = 0;
  43
  44         smp_write_processors(mc);
  45
  46         get_bus_conf();
  47
  48         m = sysconf.mb;
  49
  50 /*Bus:          Bus ID  Type*/
  51        /* define bus and isa numbers */
  52         for(bus_num = 0; bus_num < m->bus_isa; bus_num++) {
  53                 smp_write_bus(mc, bus_num, "PCI   ");
  54         }
  55         smp_write_bus(mc, m->bus_isa, "ISA   ");
  56
  57 /*I/O APICs:    APIC ID Version State           Address*/
  58         smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111
  59         {
  60                 device_t dev;
  61                 struct resource *res;
  62                 dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1));
  63                 if (dev) {
  64                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
  65                         if (res) {
  66                                 smp_write_ioapic(mc, m->apicid_8132_1, 0x11, res->base);
  67                         }
  68                 }
  69                 dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1));
  70                 if (dev) {
  71                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
  72                         if (res) {
  73                                 smp_write_ioapic(mc, m->apicid_8132_2, 0x11, res->base);
  74                         }
  75                 }
  76
  77                 j = 0;
  78
  79                 for(i=1; i< sysconf.hc_possible_num; i++) {
  80                         if(!(sysconf.pci1234[i] & 0x1) ) continue;
  81
  82                         switch(sysconf.hcid[i]) {
  83                         case 1: // 8132
  84                         case 3: // 8131
  85                                 dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
  86                                 if (dev) {
  87                                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
  88                                         if (res) {
  89                                                 smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11, res->base);
  90                                         }
  91                                 }
  92                                 dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
  93                                 if (dev) {
  94                                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
  95                                         if (res) {
  96                                                 smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11, res->base);
  97                                         }
  98                                 }
  99                                 break;
 100                         }
 101                         j++;
 102                 }
 103
 104         }
 105
 106         mptable_add_isa_interrupts(mc, m->bus_isa, m->apicid_8111, 0);
 107
 108 /*I/O Ints:     Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
 109 //??? What
 110         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13);
 111
 112 // Onboard AMD USB
 113         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0<<2)|3, m->apicid_8111, 0x13);
 114
 115 //Slot 3  PCI 32
 116         for(i=0;i<4;i++) {
 117                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5<<2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16
 118         }
 119
 120
 121 //Slot 4 PCI 32
 122         for(i=0;i<4;i++) {
 123                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4<<2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16
 124         }
 125
 126
 127 //Slot 1 PCI-X 133/100/66
 128         for(i=0;i<4;i++) {
 129                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (1<<2)|i, m->apicid_8132_2, (0+i)%4); //
 130         }
 131
 132
 133 //Slot 2 PCI-X 133/100/66
 134         for(i=0;i<4;i++) {
 135                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1<<2)|i, m->apicid_8132_1, (1+i)%4); //25
 136         }
 137
 138         j = 0;
 139
 140         for(i=1; i< sysconf.hc_possible_num; i++) {
 141                 if(!(sysconf.pci1234[i] & 0x1) ) continue;
 142                 int ii;
 143                 device_t dev;
 144                 struct resource *res;
 145                 switch(sysconf.hcid[i]) {
 146                 case 1:
 147                 case 3:
 148                         dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
 149                         if (dev) {
 150                                 res = find_resource(dev, PCI_BASE_ADDRESS_0);
 151                                 if (res) {
 152                                         //Slot 1 PCI-X 133/100/66
 153                                         for(ii=0;ii<4;ii++) {
 154                                                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0<<2)|ii, m->apicid_8132a[j][0], (0+ii)%4); //
 155                                         }
 156                                 }
 157                         }
 158
 159                         dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
 160                         if (dev) {
 161                                 res = find_resource(dev, PCI_BASE_ADDRESS_0);
 162                                 if (res) {
 163                                         //Slot 2 PCI-X 133/100/66
 164                                         for(ii=0;ii<4;ii++) {
 165                                                 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0<<2)|ii, m->apicid_8132a[j][1], (0+ii)%4); //25
 166                                         }
 167                                 }
 168                         }
 169
 170                         break;
 171                 case 2:
 172
 173                 //  Slot AGP
 174                         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151[j][1], 0x0, m->apicid_8111, 0x11);
 175                         break;
 176                 }
 177
 178                 j++;
 179         }
 180
 181
 182
 183 /*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN#*/
 184         smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);
 185         smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1);
 186         /* There is no extension information... */
 187
 188         /* Compute the checksums */
 189         mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 190         mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
 191         printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 192                 mc, smp_next_mpe_entry(mc));
 193         return smp_next_mpe_entry(mc);
 194 }
 195
 196 unsigned long write_smp_table(unsigned long addr)
 197 {
 198         void *v;
 199         v = smp_write_floating_table(addr);
 200         return (unsigned long)smp_write_config_table(v);
 201 }