4 #define RAMINIT_SYSINFO 1
5 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
7 #define SET_NB_CFG_54 1
10 #define QRANK_DIMM_SUPPORT 1
12 //used by incoherent_ht
13 //#define K8_SCAN_PCI_BUS 1
14 //#define K8_ALLOCATE_IO_RANGE 1
17 //used by init_cpus and fidvid
18 #define K8_SET_FIDVID 0
19 //if we want to wait for core1 done before DQS training, set it to 0
20 #define K8_SET_FIDVID_CORE0_ONLY 1
22 #if K8_REV_F_SUPPORT == 1
23 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
28 #include <device/pci_def.h>
29 #include <device/pci_ids.h>
31 #include <device/pnp_def.h>
32 #include <arch/romcc_io.h>
33 #include <cpu/x86/lapic.h>
34 #include "option_table.h"
35 #include "pc80/mc146818rtc_early.c"
39 static void post_code(uint8_t value) {
42 for(i=0;i<0x80000;i++) {
48 #if USE_FAILOVER_IMAGE==0
49 #include "pc80/serial.c"
50 #include "arch/i386/lib/console.c"
51 #include <cpu/amd/model_fxx_rev.h>
52 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
53 #include "northbridge/amd/amdk8/raminit.h"
54 #include "cpu/amd/model_fxx/apic_timer.c"
59 #include "cpu/x86/lapic/boot_cpu.c"
60 #include "northbridge/amd/amdk8/reset_test.c"
62 #if USE_FAILOVER_IMAGE==0
63 #include "cpu/x86/bist.h"
65 #include "lib/delay.c"
67 #include "northbridge/amd/amdk8/debug.c"
68 #include "cpu/amd/mtrr/amd_earlymtrr.c"
69 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
71 #include "northbridge/amd/amdk8/setup_resource_map.c"
73 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
75 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
77 static void memreset_setup(void)
79 //GPIO on amd8111 to enable MEMRST ????
80 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
81 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
84 static void memreset(int controllers, const struct mem_controller *ctrl)
88 static inline void activate_spd_rom(const struct mem_controller *ctrl)
90 #define SMBUS_HUB 0x18
92 unsigned device=(ctrl->channel0[0])>>8;
93 /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
96 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
97 } while ((ret!=0) && (i-->0));
99 smbus_write_byte(SMBUS_HUB, 0x03, 0);
102 static inline void change_i2c_mux(unsigned device)
104 #define SMBUS_HUB 0x18
106 print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\r\n");
109 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
110 print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\r\n");
111 } while ((ret!=0) && (i-->0));
112 ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
113 print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\r\n");
117 static inline int spd_read_byte(unsigned device, unsigned address)
119 return smbus_read_byte(device, address);
122 #include "northbridge/amd/amdk8/amdk8.h"
123 #include "northbridge/amd/amdk8/coherent_ht.c"
125 #include "northbridge/amd/amdk8/incoherent_ht.c"
127 #include "northbridge/amd/amdk8/raminit_f.c"
129 #include "sdram/generic_sdram.c"
131 /* tyan does not want the default */
132 #include "resourcemap.c"
134 #include "cpu/amd/dualcore/dualcore.c"
136 #define RC0 ((1<<0)<<8)
137 #define RC1 ((1<<1)<<8)
138 #define RC2 ((1<<2)<<8)
139 #define RC3 ((1<<3)<<8)
151 #include "cpu/amd/car/copy_and_run.c"
152 #include "cpu/amd/car/post_cache_as_ram.c"
154 #include "cpu/amd/model_fxx/init_cpus.c"
156 #include "cpu/amd/model_fxx/fidvid.c"
159 #if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
161 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
162 #include "northbridge/amd/amdk8/early_ht.c"
164 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
167 unsigned last_boot_normal_x = last_boot_normal();
169 /* Is this a cpu only reset? or Is this a secondary cpu? */
170 if ((cpu_init_detectedx) || (!boot_cpu())) {
171 if (last_boot_normal_x) {
178 /* Nothing special needs to be done to find bus 0 */
179 /* Allow the HT devices to be found */
181 enumerate_ht_chain();
183 /* Setup the rom access for 4M */
184 amd8111_enable_rom();
186 /* Is this a deliberate reset by the bios */
187 if (bios_reset_detected() && last_boot_normal_x) {
190 /* This is the primary cpu how should I boot? */
191 else if (do_normal_boot()) {
198 __asm__ volatile ("jmp __normal_image"
200 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
204 #if HAVE_FAILOVER_BOOT==1
205 __asm__ volatile ("jmp __fallback_image"
207 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
214 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
216 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
218 #if HAVE_FAILOVER_BOOT==1
219 #if USE_FAILOVER_IMAGE==1
220 failover_process(bist, cpu_init_detectedx);
222 real_main(bist, cpu_init_detectedx);
225 #if USE_FALLBACK_IMAGE == 1
226 failover_process(bist, cpu_init_detectedx);
228 real_main(bist, cpu_init_detectedx);
232 #if USE_FAILOVER_IMAGE==0
234 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
236 static const uint16_t spd_addr[] = {
238 RC0|DIMM0, RC0|DIMM2, 0, 0,
239 RC0|DIMM1, RC0|DIMM3, 0, 0,
240 #if CONFIG_MAX_PHYSICAL_CPUS > 1
242 RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6,
243 RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7,
245 #if CONFIG_MAX_PHYSICAL_CPUS > 2
247 RC2|DIMM0, RC2|DIMM2, 0, 0,
248 RC2|DIMM1, RC2|DIMM3, 0, 0,
250 RC3|DIMM0, RC3|DIMM2, RC3|DIMM4, RC3|DIMM6,
251 RC3|DIMM1, RC3|DIMM3, RC3|DIMM5, RC3|DIMM7,
256 struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
258 int needs_reset; int i;
259 unsigned bsp_apicid = 0;
260 struct cpuid_result cpuid1;
263 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
268 w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
272 // dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE);
274 /* Halt if there was a built in self test failure */
275 report_bist_failure(bist);
277 print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(","); print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
279 setup_mb_resource_map();
281 dump_pci_device(PCI_DEV(0, 0x18, 0));
282 dump_pci_device(PCI_DEV(0, 0x19, 0));
285 print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
287 #if MEM_TRAIN_SEQ == 1
288 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
290 setup_coherent_ht_domain(); // routing table and start other core0
292 wait_all_core0_started();
293 #if CONFIG_LOGICAL_CPUS==1
294 // It is said that we should start core1 after all core0 launched
295 /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
296 * So here need to make sure last core0 is started, esp for two way system,
297 * (there may be apic id conflicts in that case)
300 wait_all_other_cores_started(bsp_apicid);
303 /* it will set up chains and store link pair for optimization later */
304 ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
307 //it your CPU min fid is 1G, you can change HT to 1G and FID to max one time.
308 needs_reset = optimize_link_coherent_ht();
309 needs_reset |= optimize_link_incoherent_ht(sysinfo);
312 #if K8_SET_FIDVID == 1
313 /* Check to see if processor is capable of changing FIDVID */
314 /* otherwise it will throw a GP# when reading FIDVID_STATUS */
315 cpuid1 = cpuid(0x80000007);
316 if( (cpuid1.edx & 0x6) == 0x6 ) {
319 /* Read FIDVID_STATUS */
321 msr=rdmsr(0xc0010042);
322 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
328 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
330 init_fidvid_bsp(bsp_apicid);
332 // show final fid and vid
335 msr=rdmsr(0xc0010042);
336 print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
341 print_debug("Changing FIDVID not supported\n");
347 needs_reset = optimize_link_coherent_ht();
348 needs_reset |= optimize_link_incoherent_ht(sysinfo);
350 // fidvid change will issue one LDTSTOP and the HT change will be effective too
352 print_info("ht reset -\r\n");
353 soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
356 allow_all_aps_stop(bsp_apicid);
358 //It's the time to set ctrl in sysinfo now;
359 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
365 activate_spd_rom(&cpu[i]);
366 dump_smbus_registers();
371 for(i=1;i<256;i<<=1) {
373 dump_smbus_registers();
379 //do we need apci timer, tsc...., only debug need it for better output
380 /* all ap stopped? */
381 // init_timer(); // Need to use TMICT to synconize FID/VID
383 sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
390 // dump_pci_devices();
391 dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98);
392 dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98);
395 post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now