src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c

   1 #define ASSEMBLY 1
   2 #define __ROMCC__
   3
   4 #define RAMINIT_SYSINFO 1
   5 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
   6
   7 #define SET_NB_CFG_54 1
   8
   9 //used by raminit
  10 #define QRANK_DIMM_SUPPORT 1
  11
  12 //used by incoherent_ht
  13 //#define K8_SCAN_PCI_BUS 1
  14 //#define K8_ALLOCATE_IO_RANGE 1
  15
  16
  17 //used by init_cpus and fidvid
  18 #define K8_SET_FIDVID 0
  19 //if we want to wait for core1 done before DQS training, set it to 0
  20 #define K8_SET_FIDVID_CORE0_ONLY 1
  21
  22 #if K8_REV_F_SUPPORT == 1
  23 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
  24 #endif
  25
  26 #include <stdint.h>
  27 #include <device/pci_def.h>
  28 #include <device/pci_ids.h>
  29 #include <arch/io.h>
  30 #include <device/pnp_def.h>
  31 #include <arch/romcc_io.h>
  32 #include <cpu/x86/lapic.h>
  33 #include "option_table.h"
  34 #include "pc80/mc146818rtc_early.c"
  35
  36 #if 0
  37 static void post_code(uint8_t value) {
  38 #if 1
  39         int i;
  40         for(i=0;i<0x80000;i++) {
  41                 outb(value, 0x80);
  42         }
  43 #endif
  44 }
  45 #endif
  46 #if USE_FAILOVER_IMAGE==0
  47 #include "pc80/serial.c"
  48 #include "arch/i386/lib/console.c"
  49 #include <cpu/amd/model_fxx_rev.h>
  50 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  51 #include "northbridge/amd/amdk8/raminit.h"
  52 #include "cpu/amd/model_fxx/apic_timer.c"
  53 #endif
  54
  55
  56
  57 #include "cpu/x86/lapic/boot_cpu.c"
  58 #include "northbridge/amd/amdk8/reset_test.c"
  59
  60 #if USE_FAILOVER_IMAGE==0
  61 #include "cpu/x86/bist.h"
  62
  63 #include "lib/delay.c"
  64
  65 #if CONFIG_USE_INIT == 0
  66         #include "lib/memcpy.c"
  67  #if CONFIG_USE_PRINTK_IN_CAR == 1
  68         #include "lib/uart8250.c"
  69         #include "console/vtxprintf.c"
  70         #include "arch/i386/lib/printk_init.c"
  71  #endif
  72 #endif
  73 #include "northbridge/amd/amdk8/debug.c"
  74 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  75 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  76
  77 #include "northbridge/amd/amdk8/setup_resource_map.c"
  78
  79 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  80
  81 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  82
  83 static void memreset_setup(void)
  84 {
  85         //GPIO on amd8111 to enable MEMRST ????
  86         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  87         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  88 }
  89
  90 static void memreset(int controllers, const struct mem_controller *ctrl)
  91 {
  92 }
  93
  94 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  95 {
  96 #define SMBUS_HUB 0x18
  97         int ret,i;
  98         unsigned device=(ctrl->channel0[0])>>8;
  99         /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
 100         i=2;
 101         do {
 102                 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
 103         } while ((ret!=0) && (i-->0));
 104
 105         smbus_write_byte(SMBUS_HUB, 0x03, 0);
 106 }
 107 #if 0
 108 static inline void change_i2c_mux(unsigned device)
 109 {
 110 #define SMBUS_HUB 0x18
 111         int ret, i;
 112         print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\r\n");
 113         i=2;
 114         do {
 115                 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
 116                 print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\r\n");
 117         } while ((ret!=0) && (i-->0));
 118         ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
 119         print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\r\n");
 120 }
 121 #endif
 122
 123 static inline int spd_read_byte(unsigned device, unsigned address)
 124 {
 125         return smbus_read_byte(device, address);
 126 }
 127
 128 #include "northbridge/amd/amdk8/amdk8.h"
 129 #include "northbridge/amd/amdk8/coherent_ht.c"
 130
 131 #include "northbridge/amd/amdk8/incoherent_ht.c"
 132
 133 #include "northbridge/amd/amdk8/raminit.c"
 134
 135 #include "sdram/generic_sdram.c"
 136
 137  /* tyan does not want the default */
 138 #include "resourcemap.c"
 139
 140 #include "cpu/amd/dualcore/dualcore.c"
 141
 142 #define RC0 ((1<<0)<<8)
 143 #define RC1 ((1<<1)<<8)
 144 #define RC2 ((1<<2)<<8)
 145 #define RC3 ((1<<3)<<8)
 146
 147 #define DIMM0 0x50
 148 #define DIMM1 0x51
 149 #define DIMM2 0x52
 150 #define DIMM3 0x53
 151 #define DIMM4 0x54
 152 #define DIMM5 0x55
 153 #define DIMM6 0x56
 154 #define DIMM7 0x57
 155
 156
 157 #include "cpu/amd/car/copy_and_run.c"
 158 #include "cpu/amd/car/post_cache_as_ram.c"
 159
 160 #include "cpu/amd/model_fxx/init_cpus.c"
 161
 162 #include "cpu/amd/model_fxx/fidvid.c"
 163 #endif
 164
 165 #if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
 166
 167 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 168 #include "northbridge/amd/amdk8/early_ht.c"
 169
 170 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 171 {
 172
 173         unsigned last_boot_normal_x = last_boot_normal();
 174
 175         /* Is this a cpu only reset? or Is this a secondary cpu? */
 176         if ((cpu_init_detectedx) || (!boot_cpu())) {
 177                 if (last_boot_normal_x) {
 178                         goto normal_image;
 179                 } else {
 180                         goto fallback_image;
 181                 }
 182         }
 183
 184         /* Nothing special needs to be done to find bus 0 */
 185         /* Allow the HT devices to be found */
 186
 187         enumerate_ht_chain();
 188
 189         /* Setup the rom access for 4M */
 190         amd8111_enable_rom();
 191
 192         /* Is this a deliberate reset by the bios */
 193         if (bios_reset_detected() && last_boot_normal_x) {
 194                 goto normal_image;
 195         }
 196         /* This is the primary cpu how should I boot? */
 197         else if (do_normal_boot()) {
 198                 goto normal_image;
 199         }
 200         else {
 201                 goto fallback_image;
 202         }
 203  normal_image:
 204         __asm__ volatile ("jmp __normal_image"
 205                 : /* outputs */
 206                 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
 207                 );
 208
 209  fallback_image:
 210 #if HAVE_FAILOVER_BOOT==1
 211         __asm__ volatile ("jmp __fallback_image"
 212                 : /* outputs */
 213                 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
 214                 )
 215 #endif
 216         ;
 217 }
 218 #endif
 219
 220 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 221
 222 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 223 {
 224 #if HAVE_FAILOVER_BOOT==1
 225     #if USE_FAILOVER_IMAGE==1
 226         failover_process(bist, cpu_init_detectedx);
 227     #else
 228         real_main(bist, cpu_init_detectedx);
 229     #endif
 230 #else
 231     #if USE_FALLBACK_IMAGE == 1
 232         failover_process(bist, cpu_init_detectedx);
 233     #endif
 234         real_main(bist, cpu_init_detectedx);
 235 #endif
 236 }
 237
 238 #if USE_FAILOVER_IMAGE==0
 239
 240 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 241 {
 242         static const uint16_t spd_addr[] = {
 243                         //first node
 244                         RC0|DIMM0, RC0|DIMM2, 0, 0,
 245                         RC0|DIMM1, RC0|DIMM3, 0, 0,
 246 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 247                         //second node
 248                         RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6,
 249                         RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7,
 250 #endif
 251 #if CONFIG_MAX_PHYSICAL_CPUS > 2
 252                         // third node
 253                         RC2|DIMM0, RC2|DIMM2, 0, 0,
 254                         RC2|DIMM1, RC2|DIMM3, 0, 0,
 255                         // four node
 256                         RC3|DIMM0, RC3|DIMM2, RC3|DIMM4, RC3|DIMM6,
 257                         RC3|DIMM1, RC3|DIMM3, RC3|DIMM5, RC3|DIMM7,
 258 #endif
 259
 260         };
 261
 262         struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
 263
 264         int needs_reset; int i;
 265         unsigned bsp_apicid = 0;
 266
 267         if (bist == 0) {
 268                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 269         }
 270
 271 //      post_code(0x32);
 272
 273         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
 274         uart_init();
 275         console_init();
 276
 277 //      dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE);
 278
 279         /* Halt if there was a built in self test failure */
 280         report_bist_failure(bist);
 281
 282         print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(",");  print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
 283
 284         setup_mb_resource_map();
 285 #if 0
 286         dump_pci_device(PCI_DEV(0, 0x18, 0));
 287         dump_pci_device(PCI_DEV(0, 0x19, 0));
 288 #endif
 289
 290         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
 291
 292 #if MEM_TRAIN_SEQ == 1
 293         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 294 #endif
 295         setup_coherent_ht_domain(); // routing table and start other core0
 296
 297         wait_all_core0_started();
 298 #if CONFIG_LOGICAL_CPUS==1
 299         // It is said that we should start core1 after all core0 launched
 300         /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 301          * So here need to make sure last core0 is started, esp for two way system,
 302          * (there may be apic id conflicts in that case)
 303          */
 304         start_other_cores();
 305         wait_all_other_cores_started(bsp_apicid);
 306 #endif
 307
 308         /* it will set up chains and store link pair for optimization later */
 309         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 310
 311 #if 0
 312         //it your CPU min fid is 1G, you can change HT to 1G and FID to max one time.
 313         needs_reset = optimize_link_coherent_ht();
 314         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 315 #endif
 316
 317 #if K8_SET_FIDVID == 1
 318
 319         {
 320                 msr_t msr;
 321                 msr=rdmsr(0xc0010042);
 322                 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
 323
 324         }
 325
 326         enable_fid_change();
 327
 328         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 329
 330         init_fidvid_bsp(bsp_apicid);
 331
 332         // show final fid and vid
 333         {
 334                 msr_t msr;
 335                 msr=rdmsr(0xc0010042);
 336                 print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
 337
 338         }
 339 #endif
 340
 341 #if 1
 342         needs_reset = optimize_link_coherent_ht();
 343         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 344
 345         // fidvid change will issue one LDTSTOP and the HT change will be effective too
 346         if (needs_reset) {
 347                 print_info("ht reset -\r\n");
 348                 soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
 349         }
 350 #endif
 351         allow_all_aps_stop(bsp_apicid);
 352
 353         //It's the time to set ctrl in sysinfo now;
 354         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 355
 356         enable_smbus();
 357
 358 #if 0
 359         for(i=0;i<4;i++) {
 360                 activate_spd_rom(&cpu[i]);
 361                 dump_smbus_registers();
 362         }
 363 #endif
 364
 365 #if 0
 366         for(i=1;i<256;i<<=1) {
 367                 change_i2c_mux(i);
 368                 dump_smbus_registers();
 369         }
 370 #endif
 371
 372         memreset_setup();
 373
 374         //do we need apci timer, tsc...., only debug need it for better output
 375         /* all ap stopped? */
 376 //        init_timer(); // Need to use TMICT to synconize FID/VID
 377
 378         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 379
 380 #if 0
 381         print_pci_devices();
 382 #endif
 383
 384 #if 0
 385 //        dump_pci_devices();
 386         dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98);
 387         dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98);
 388 #endif
 389
 390         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
 391
 392 }
 393 #endif