4 #define RAMINIT_SYSINFO 1
5 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
7 #define SET_NB_CFG_54 1
10 #define QRANK_DIMM_SUPPORT 1
12 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
15 #include <device/pci_def.h>
16 #include <device/pci_ids.h>
18 #include <device/pnp_def.h>
19 #include <arch/romcc_io.h>
20 #include <cpu/x86/lapic.h>
21 #include "option_table.h"
22 #include "pc80/mc146818rtc_early.c"
23 #include "pc80/serial.c"
24 #include "./arch/i386/lib/printk_init.c"
26 #include "console/console.c"
27 #include "lib/uart8250.c"
28 #include "console/vtxprintf.c"
30 #include <cpu/amd/model_fxx_rev.h>
31 #include "northbridge/amd/amdk8/raminit.h"
32 #include "cpu/amd/model_fxx/apic_timer.c"
34 #include "lib/delay.c"
37 //#include "cpu/x86/lapic/boot_cpu.c"
38 #include "northbridge/amd/amdk8/reset_test.c"
40 #include "northbridge/amd/amdk8/debug.c"
42 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
44 #include "northbridge/amd/amdk8/amdk8_f.h"
46 #include "cpu/x86/mtrr.h"
47 #include "cpu/amd/mtrr.h"
48 #include "cpu/x86/tsc.h"
50 #include "northbridge/amd/amdk8/amdk8_f_pci.c"
51 #include "northbridge/amd/amdk8/raminit_f_dqs.c"
53 static inline unsigned get_nodes(void)
55 return ((pci_read_config32(PCI_DEV(0, 0x18, 0), 0x60)>>4) & 7) + 1;
58 #include "cpu/amd/dualcore/dualcore.c"
60 void hardwaremain(int ret_addr)
62 struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
63 struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
65 struct node_core_id id;
67 id = get_node_core_id_x();
69 #if CONFIG_USE_PRINTK_IN_CAR
70 printk(BIOS_DEBUG, "CODE IN CACHE ON NODE: %02x\n");
72 print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n");
75 train_ram(id.nodeid, sysinfo, sysinfox);
78 go back, but can not use stack any more, because we only keep ret_addr and can not restore esp, and ebp
91 #include <arch/registers.h>
93 void x86_exception(struct eregs *info)