5 uses USE_FALLBACK_IMAGE
6 uses USE_FAILOVER_IMAGE
7 uses HAVE_FALLBACK_BOOT
8 uses HAVE_FAILOVER_BOOT
11 uses HAVE_OPTION_TABLE
13 uses CONFIG_MAX_PHYSICAL_CPUS
14 uses CONFIG_LOGICAL_CPUS
23 uses ROM_SECTION_OFFSET
24 uses CONFIG_ROM_PAYLOAD
25 uses CONFIG_ROM_PAYLOAD_START
26 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
27 uses CONFIG_PRECOMPRESSED_PAYLOAD
35 uses LB_CKS_RANGE_START
38 uses MAINBOARD_PART_NUMBER
41 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
42 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
43 uses COREBOOT_EXTRA_VERSION
48 uses DEFAULT_CONSOLE_LOGLEVEL
49 uses MAXIMUM_CONSOLE_LOGLEVEL
50 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
51 uses CONFIG_CONSOLE_SERIAL8250
60 uses CONFIG_CONSOLE_VGA
61 uses CONFIG_PCI_ROM_RUN
62 uses HW_MEM_HOLE_SIZEK
63 uses HW_MEM_HOLE_SIZE_AUTO_INC
64 uses K8_HT_FREQ_1G_SUPPORT
66 uses HT_CHAIN_UNITID_BASE
67 uses HT_CHAIN_END_UNITID_BASE
68 uses SB_HT_CHAIN_ON_BUS0
69 uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
74 uses DCACHE_RAM_GLOBAL_VAR_SIZE
79 uses ENABLE_APIC_EXT_ID
83 uses CONFIG_PCI_64BIT_PREF_MEM
85 uses CONFIG_LB_MEM_TOPK
87 uses CONFIG_AP_CODE_IN_CAR
91 uses WAIT_BEFORE_CPUS_INIT
93 uses CONFIG_USE_PRINTK_IN_CAR
100 ## ROM_SIZE is the size of boot ROM that this board will use.
102 default ROM_SIZE=524288
105 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
107 #default FALLBACK_SIZE=131072
108 #default FALLBACK_SIZE=0x40000
111 default FALLBACK_SIZE=0x3f000
113 default FAILOVER_SIZE=0x01000
116 default CONFIG_LB_MEM_TOPK=2048
119 ## Build code for the fallback boot
121 default HAVE_FALLBACK_BOOT=1
122 default HAVE_FAILOVER_BOOT=1
125 ## Build code to reset the motherboard from coreboot
127 default HAVE_HARD_RESET=1
130 ## Build code to export a programmable irq routing table
132 default HAVE_PIRQ_TABLE=1
133 default IRQ_SLOT_COUNT=11
136 ## Build code to export an x86 MP table
137 ## Useful for specifying IRQ routing values
139 default HAVE_MP_TABLE=1
141 ## ACPI tables will be included
142 default HAVE_ACPI_TABLES=1
144 default ACPI_SSDTX_NUM=1
147 ## Build code to export a CMOS option table
149 default HAVE_OPTION_TABLE=1
152 ## Move the default coreboot cmos range off of AMD RTC registers
154 default LB_CKS_RANGE_START=49
155 default LB_CKS_RANGE_END=122
156 default LB_CKS_LOC=123
159 ## Build code for SMP support
160 ## Only worry about 2 micro processors
163 default CONFIG_MAX_CPUS=8
164 default CONFIG_MAX_PHYSICAL_CPUS=4
165 default CONFIG_LOGICAL_CPUS=1
167 default SERIAL_CPU_INIT=0
169 default ENABLE_APIC_EXT_ID=0
170 default APIC_ID_OFFSET=0x8
171 default LIFT_BSP_APIC_ID=1
174 default CONFIG_CHIP_NAME=1
176 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
178 #default HW_MEM_HOLE_SIZEK=0x200000
180 default HW_MEM_HOLE_SIZEK=0x100000
182 #default HW_MEM_HOLE_SIZEK=0x80000
184 #make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
185 #default HW_MEM_HOLE_SIZE_AUTO_INC=1
187 #Opteron K8 1G HT Support
188 default K8_HT_FREQ_1G_SUPPORT=1
191 default CONFIG_CONSOLE_VGA=1
192 default CONFIG_PCI_ROM_RUN=1
194 #HT Unit ID offset, default is 1, the typical one
195 default HT_CHAIN_UNITID_BASE=0xa
197 #real SB Unit ID, default is 0x20, mean dont touch it at last
198 default HT_CHAIN_END_UNITID_BASE=0x6
200 #make the SB HT chain on bus 0, default is not (0)
201 default SB_HT_CHAIN_ON_BUS0=2
203 #only offset for SB chain?, default is yes(1)
204 #default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
206 #allow capable device use that above 4G
207 #default CONFIG_PCI_64BIT_PREF_MEM=1
210 ## enable CACHE_AS_RAM specifics
212 default USE_DCACHE_RAM=1
213 default DCACHE_RAM_BASE=0xc8000
214 default DCACHE_RAM_SIZE=0x08000
215 default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
216 default CONFIG_USE_INIT=0
220 ## for rev F training on AP purpose
222 default CONFIG_AP_CODE_IN_CAR=1
223 default MEM_TRAIN_SEQ=1
224 default WAIT_BEFORE_CPUS_INIT=1
227 ## Build code to setup a generic IOAPIC
229 default CONFIG_IOAPIC=1
232 ## Clean up the motherboard id strings
234 default MAINBOARD_PART_NUMBER="serengeti_cheetah"
235 default MAINBOARD_VENDOR="AMD"
236 default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
237 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
240 ### coreboot layout values
243 ## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
244 default ROM_IMAGE_SIZE = 65536
247 ## Use a small 8K stack
249 default STACK_SIZE=0x2000
252 ## Use a small 32K heap
254 default HEAP_SIZE=0x8000
257 ## Only use the option table in a normal image
259 default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
262 ## Coreboot C code runs at this location in RAM
264 default _RAMBASE=0x00100000
267 ## Load the payload from the ROM
269 default CONFIG_ROM_PAYLOAD = 1
272 ### Defaults of options that you may want to override in the target config file
276 ## The default compiler
278 default CC="$(CROSS_COMPILE)gcc -m32"
282 ## Disable the gdb stub by default
284 default CONFIG_GDB_STUB=0
287 ## The Serial Console
289 default CONFIG_USE_PRINTK_IN_CAR=0
291 # To Enable the Serial Console
292 default CONFIG_CONSOLE_SERIAL8250=1
294 ## Select the serial console baud rate
295 default TTYS0_BAUD=115200
296 #default TTYS0_BAUD=57600
297 #default TTYS0_BAUD=38400
298 #default TTYS0_BAUD=19200
299 #default TTYS0_BAUD=9600
300 #default TTYS0_BAUD=4800
301 #default TTYS0_BAUD=2400
302 #default TTYS0_BAUD=1200
304 # Select the serial console base port
305 default TTYS0_BASE=0x3f8
307 # Select the serial protocol
308 # This defaults to 8 data bits, 1 stop bit, and no parity
309 default TTYS0_LCS=0x3
312 ### Select the coreboot loglevel
314 ## EMERG 1 system is unusable
315 ## ALERT 2 action must be taken immediately
316 ## CRIT 3 critical conditions
317 ## ERR 4 error conditions
318 ## WARNING 5 warning conditions
319 ## NOTICE 6 normal but significant condition
320 ## INFO 7 informational
321 ## DEBUG 8 debug-level messages
322 ## SPEW 9 Way too many details
324 ## Request this level of debugging output
325 default DEFAULT_CONSOLE_LOGLEVEL=8
326 ## At a maximum only compile in this level of debugging
327 default MAXIMUM_CONSOLE_LOGLEVEL=8
330 ## Select power on after power fail setting
331 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"