src/mainboard/amd/rumba/romstage.c

   1 #include <stdint.h>
   2 #include <device/pci_def.h>
   3 #include <arch/io.h>
   4 #include <device/pnp_def.h>
   5 #include <arch/hlt.h>
   6 #include <console/console.h>
   7 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
   8 #include "cpu/x86/bist.h"
   9 #include "cpu/x86/msr.h"
  10 #include <cpu/amd/gx2def.h>
  11 #include <cpu/amd/geode_post_code.h>
  12 #include <spd.h>
  13
  14 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  15
  16 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
  17 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
  18
  19 static inline int spd_read_byte(unsigned device, unsigned address)
  20 {
  21         if (device != DIMM0)
  22                 return 0xFF;    /* No DIMM1, don't even try. */
  23
  24         return smbus_read_byte(device, address);
  25 }
  26
  27 #include "northbridge/amd/gx2/raminit.h"
  28 #include "northbridge/amd/gx2/pll_reset.c"
  29 #include "northbridge/amd/gx2/raminit.c"
  30 #include "lib/generic_sdram.c"
  31 #include "cpu/amd/model_gx2/cpureginit.c"
  32 #include "cpu/amd/model_gx2/syspreinit.c"
  33 #include "cpu/amd/model_lx/msrinit.c"
  34
  35 void main(unsigned long bist)
  36 {
  37         static const struct mem_controller memctrl [] = {
  38                 {.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
  39         };
  40
  41         SystemPreInit();
  42
  43         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
  44         uart_init();
  45         console_init();
  46
  47         cs5536_early_setup();
  48
  49         /* Halt if there was a built in self test failure */
  50         report_bist_failure(bist);
  51
  52         pll_reset();
  53
  54         cpuRegInit();
  55         print_err("done cpuRegInit\n");
  56
  57         sdram_initialize(1, memctrl);
  58
  59         msr_init();
  60
  61         /* Check all of memory */
  62         //ram_check(0x00000000, 640*1024);
  63 }
  64