2 #include <device/pci_def.h>
4 #include <device/pnp_def.h>
6 #include <console/console.h>
7 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
8 #include "cpu/x86/bist.h"
9 #include "cpu/x86/msr.h"
10 #include <cpu/amd/gx2def.h>
11 #include <cpu/amd/geode_post_code.h>
13 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
15 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
16 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
18 static inline int spd_read_byte(unsigned device, unsigned address)
20 return smbus_read_byte(device, address);
23 #include "northbridge/amd/gx2/raminit.h"
25 static inline unsigned int fls(unsigned int x)
29 __asm__("bsfl %1,%0\n\t"
32 "1:" : "=r" (r) : "g" (x));
36 static void sdram_set_spd_registers(const struct mem_controller *ctrl)
38 /* Total size of DIMM = 2^row address (byte 3) * 2^col address (byte 4) *
39 * component Banks (byte 17) * module banks, side (byte 5) *
40 * width in bits (byte 6,7)
41 * = Density per side (byte 31) * number of sides (byte 5) */
42 /* 1. Initialize GLMC registers base on SPD values, do one DIMM for now */
44 unsigned char module_banks, val;
46 msr = rdmsr(MC_CF07_DATA);
48 /* get module banks (sides) per dimm, SPD byte 5 */
49 module_banks = spd_read_byte(0xA0, 5);
50 if (module_banks < 1 || module_banks > 2)
51 print_err("Module banks per dimm\n");
53 msr.hi &= ~(1 << CF07_UPPER_D0_MB_SHIFT);
54 msr.hi |= (module_banks << CF07_UPPER_D0_MB_SHIFT);
56 /* get component banks per module bank, SPD byte 17 */
57 val = spd_read_byte(0xA0, 17);
58 if (val < 2 || val > 4)
59 print_err("Component banks per module bank\n");
61 msr.hi &= ~(0x1 << CF07_UPPER_D0_CB_SHIFT);
62 msr.hi |= (val << CF07_UPPER_D0_CB_SHIFT);
64 /* get the module bank density, SPD byte 31 */
65 val = spd_read_byte(0xA0, 31);
68 msr.hi &= ~(0xf << CF07_UPPER_D0_SZ_SHIFT);
69 msr.hi |= (val << CF07_UPPER_D0_SZ_SHIFT);
71 /* page size = 2^col address */
72 val = spd_read_byte(0xA0, 4);
74 msr.hi &= ~(0x7 << CF07_UPPER_D0_PSZ_SHIFT);
75 msr.hi |= (val << CF07_UPPER_D0_PSZ_SHIFT);
77 print_debug("computed msr.hi ");
78 print_debug_hex32(msr.hi);
82 wrmsr(MC_CF07_DATA, msr);
84 msr = rdmsr(0x20000019);
87 wrmsr(0x20000019, msr);
91 #include "northbridge/amd/gx2/raminit.c"
92 #include "lib/generic_sdram.c"
94 #define PLLMSRhi 0x00001490
95 #define PLLMSRlo 0x02000030
96 #define PLLMSRlo1 ((0xde << 16) | (1 << 26) | (1 << 24))
97 #define PLLMSRlo2 ((1<<14) |(1<<13) | (1<<0))
98 #include "northbridge/amd/gx2/pll_reset.c"
99 #include "cpu/amd/model_gx2/cpureginit.c"
100 #include "cpu/amd/model_gx2/syspreinit.c"
101 #include "cpu/amd/model_lx/msrinit.c"
103 void main(unsigned long bist)
105 static const struct mem_controller memctrl [] = {
106 {.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
111 w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
115 cs5536_early_setup();
117 /* Halt if there was a built in self test failure */
118 report_bist_failure(bist);
123 print_err("done cpuRegInit\n");
125 sdram_initialize(1, memctrl);
129 /* Check all of memory */
130 //ram_check(0x00000000, 640*1024);