[coreboot.git] / src / mainboard / amd / rumba / devicetree.cb

chip northbridge/amd/gx2
        #register "irqmap" = "0xaa5b"
        device lapic_cluster 0 on
                chip cpu/amd/model_gx2
                        device lapic 0 on end
                end
        end
        device pci_domain 0 on
                device pci 1.0 on end
                device pci 1.1 on end
                chip southbridge/amd/cs5536
                        register "lpc_serirq_enable" = "0x80"  # enabled with default timing
                        device pci d.0 on end   # Realtek 8139 LAN
                        device pci f.0 on end   # ISA Bridge
                        device pci f.2 on end   # IDE Controller
                        device pci f.3 on end   # Audio
                        device pci f.4 on end   # OHCI
                        device pci f.5 on end   # EHCI
                end
        end
end