3 uses USE_FALLBACK_IMAGE
4 uses HAVE_FALLBACK_BOOT
8 uses HARD_RESET_FUNCTION
10 uses HAVE_OPTION_TABLE
19 uses ROM_SECTION_OFFSET
20 uses CONFIG_ROM_STREAM
21 uses CONFIG_ROM_STREAM_START
29 uses LB_CKS_RANGE_START
32 uses MAINBOARD_PART_NUMBER
36 ## ROM_SIZE is the size of boot ROM that this board will use.
37 default ROM_SIZE=524288
44 ## Build code for the fallback boot
46 default HAVE_FALLBACK_BOOT=1
49 ## Build code to reset the motherboard from linuxBIOS
51 default HAVE_HARD_RESET=1
53 default HARD_RESET_BUS=1
54 default HARD_RESET_DEVICE=4
55 default HARD_RESET_FUNCTION=0
58 ## Build code to export a programmable irq routing table
60 default HAVE_PIRQ_TABLE=1
61 default IRQ_SLOT_COUNT=9
64 ## Build code to export an x86 MP table
65 ## Useful for specifying IRQ routing values
67 default HAVE_MP_TABLE=1
70 ## Build code to export a CMOS option table
72 default HAVE_OPTION_TABLE=1
75 ## Move the default LinuxBIOS cmos range off of AMD RTC registers
77 default LB_CKS_RANGE_START=49
78 default LB_CKS_RANGE_END=122
79 default LB_CKS_LOC=123
82 ## Build code for SMP support
83 ## Only worry about 2 micro processors
86 default CONFIG_MAX_CPUS=4
89 ## Build code to setup a generic IOAPIC
91 default CONFIG_IOAPIC=1
94 ## Clean up the motherboard id strings
96 default MAINBOARD_PART_NUMBER="QUARTET"
97 default MAINBOARD_VENDOR="AMD"
100 ### LinuxBIOS layout values
103 ## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
104 default ROM_IMAGE_SIZE = 65536
107 ## Use a small 8K stack
109 default STACK_SIZE=0x2000
112 ## Use a small 16K heap
114 default HEAP_SIZE=0x4000
117 ## Only use the option table in a normal image
119 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
122 ## Compute the location and size of where this firmware image
123 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
125 if USE_FALLBACK_IMAGE
126 default ROM_SECTION_SIZE = FALLBACK_SIZE
127 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
129 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
130 default ROM_SECTION_OFFSET = 0
134 ## Compute the start location and size size of
135 ## The linuxBIOS bootloader.
137 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
138 default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
139 default CONFIG_ROM_STREAM = 1
142 ## Compute where this copy of linuxBIOS will start in the boot rom
144 default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
147 ## Compute a range of ROM that can cached to speed up linuxBIOS,
150 ## XIP_ROM_SIZE must be a power of 2.
151 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
153 default XIP_ROM_SIZE=65536
154 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
157 ## Set all of the defaults for an x86 architecture
164 ## Build the objects we have code for in this directory.
168 if HAVE_MP_TABLE object mptable.o end
169 if HAVE_PIRQ_TABLE object irq_tables.o end
174 makerule ./failover.E
175 depends "$(MAINBOARD)/failover.c"
176 action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
179 makerule ./failover.inc
180 depends "./failover.E ./romcc"
181 action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
185 depends "$(MAINBOARD)/auto.c option_table.h"
186 action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
189 depends "./auto.E ./romcc"
190 action "./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
194 ## Build our 16 bit and 32 bit linuxBIOS entry code
196 mainboardinit cpu/i386/entry16.inc
197 mainboardinit cpu/i386/entry32.inc
198 mainboardinit cpu/i386/bist32.inc
199 ldscript /cpu/i386/entry16.lds
200 ldscript /cpu/i386/entry32.lds
203 ## Build our reset vector (This is where linuxBIOS is entered)
205 if USE_FALLBACK_IMAGE
206 mainboardinit cpu/i386/reset16.inc
207 ldscript /cpu/i386/reset16.lds
209 mainboardinit cpu/i386/reset32.inc
210 ldscript /cpu/i386/reset32.lds
213 ### Should this be in the northbridge code?
214 mainboardinit arch/i386/lib/cpu_reset.inc
217 ## Include an id string (For safe flashing)
219 mainboardinit arch/i386/lib/id.inc
220 ldscript /arch/i386/lib/id.lds
225 mainboardinit cpu/k8/earlymtrr.inc
228 ### This is the early phase of linuxBIOS startup
229 ### Things are delicate and we test to see if we should
230 ### failover to another image.
232 if USE_FALLBACK_IMAGE
233 ldscript /arch/i386/lib/failover.lds
234 mainboardinit ./failover.inc
238 ### O.k. We aren't just an intermediary anymore!
244 mainboardinit cpu/k8/enable_mmx_sse.inc
245 mainboardinit ./auto.inc
246 mainboardinit cpu/k8/disable_mmx_sse.inc
249 ## Include the secondary Configuration files
254 northbridge amd/amdk8 "mc0"
261 southbridge amd/amd8111 "amd8111" link 2
273 superio NSC/pc87360 link 1
274 pnp 2e.0 off # Floppy
278 pnp 2e.1 off # Parallel Port
289 pnp 2e.6 on # Keyboard
301 northbridge amd/amdk8 "mc1"
308 southbridge amd/amd8131 "amd8131_0" link 1
314 southbridge amd/amd8131 "amd8131_1" link 1
322 northbridge amd/amdk8 "mc2"
331 northbridge amd/amdk8 "mc3"
353 ## Include the old serial code for those few places that still need it.
355 mainboardinit pc80/serial.inc
356 mainboardinit arch/i386/lib/console.inc
357 mainboardinit cpu/i386/bist32_fail.inc