Drop excessive whitespace randomly sprinkled in romstage.c files.
[coreboot.git] / src / mainboard / amd / pistachio / romstage.c
1 /*
2  * This file is part of the coreboot project.
3  *
4  * Copyright (C) 2008 Advanced Micro Devices, Inc.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; version 2 of the License.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
18  */
19
20 #include <stdint.h>
21 #include <string.h>
22 #include <device/pci_def.h>
23 #include <arch/io.h>
24 #include <device/pnp_def.h>
25 #include <arch/romcc_io.h>
26 #include <cpu/x86/lapic.h>
27 #include <pc80/mc146818rtc.h>
28 #include <console/console.h>
29 #include <cpu/amd/model_fxx_rev.h>
30 #include "northbridge/amd/amdk8/raminit.h"
31 #include "cpu/amd/model_fxx/apic_timer.c"
32 #include "lib/delay.c"
33 #include "cpu/x86/lapic/boot_cpu.c"
34 #include "northbridge/amd/amdk8/reset_test.c"
35 #include "superio/ite/it8712f/it8712f_early_serial.c"
36 #include <usbdebug.h>
37 #include <spd.h>
38 #include "cpu/x86/mtrr/earlymtrr.c"
39 #include "cpu/x86/bist.h"
40 #include "northbridge/amd/amdk8/setup_resource_map.c"
41 #include "southbridge/amd/rs690/rs690_early_setup.c"
42 #include "southbridge/amd/sb600/sb600_early_setup.c"
43 #include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */
44
45 /* CAN'T BE REMOVED! memory bus reset hook for some broken amd k8 boards. */
46 static void memreset(int controllers, const struct mem_controller *ctrl)
47 {
48 }
49
50 /* called in raminit_f.c */
51 static inline void activate_spd_rom(const struct mem_controller *ctrl)
52 {
53 }
54
55 /*called in raminit_f.c */
56 static inline int spd_read_byte(u32 device, u32 address)
57 {
58         return smbus_read_byte(device, address);
59 }
60
61 #include "northbridge/amd/amdk8/amdk8.h"
62 #include "northbridge/amd/amdk8/incoherent_ht.c"
63 #include "northbridge/amd/amdk8/raminit_f.c"
64 #include "northbridge/amd/amdk8/coherent_ht.c"
65 #include "lib/generic_sdram.c"
66 #include "resourcemap.c"
67 #include "cpu/amd/dualcore/dualcore.c"
68 #include "cpu/amd/car/post_cache_as_ram.c"
69 #include "cpu/amd/model_fxx/init_cpus.c"
70 #include "cpu/amd/model_fxx/fidvid.c"
71 #include "northbridge/amd/amdk8/early_ht.c"
72
73 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
74 {
75         static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
76         int needs_reset = 0;
77         u32 bsp_apicid = 0;
78         msr_t msr;
79         struct cpuid_result cpuid1;
80         struct sys_info *sysinfo =
81             (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE -
82                                 CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
83
84         if (!cpu_init_detectedx && boot_cpu()) {
85                 /* Nothing special needs to be done to find bus 0 */
86                 /* Allow the HT devices to be found */
87                 enumerate_ht_chain();
88
89                 sb600_lpc_port80();
90                 /* sb600_pci_port80(); */
91         }
92
93         if (bist == 0) {
94                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
95         }
96
97         enable_rs690_dev8();
98         sb600_lpc_init();
99
100         /* Pistachio used a FPGA to enable serial debug instead of a SIO
101          * and it doesn't require any special setup. */
102         uart_init();
103
104 #if CONFIG_USBDEBUG
105         sb600_enable_usbdebug(0);
106         early_usbdebug_init();
107 #endif
108
109         console_init();
110
111         post_code(0x03);
112
113         /* Halt if there was a built in self test failure */
114         report_bist_failure(bist);
115         printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid);
116
117         setup_pistachio_resource_map();
118
119         setup_coherent_ht_domain();
120
121 #if CONFIG_LOGICAL_CPUS==1
122         /* It is said that we should start core1 after all core0 launched */
123         wait_all_core0_started();
124         start_other_cores();
125 #endif
126         wait_all_aps_started(bsp_apicid);
127
128         /* it will set up chains and store link pair for optimization later,
129          * it will init sblnk and sbbusn, nodes, sbdn */
130         ht_setup_chains_x(sysinfo);
131
132         /* run _early_setup before soft-reset. */
133         rs690_early_setup();
134         sb600_early_setup();
135
136         post_code(0x04);
137
138         /* Check to see if processor is capable of changing FIDVID  */
139         /* otherwise it will throw a GP# when reading FIDVID_STATUS */
140         cpuid1 = cpuid(0x80000007);
141         if( (cpuid1.edx & 0x6) == 0x6 ) {
142
143                 /* Read FIDVID_STATUS */
144                 msr=rdmsr(0xc0010042);
145                 printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
146
147                 enable_fid_change();
148                 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
149                 init_fidvid_bsp(bsp_apicid);
150
151                 /* show final fid and vid */
152                 msr=rdmsr(0xc0010042);
153                 printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
154
155         } else {
156                 printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
157         }
158
159         post_code(0x05);
160
161         needs_reset = optimize_link_coherent_ht();
162         needs_reset |= optimize_link_incoherent_ht(sysinfo);
163         rs690_htinit();
164         printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
165
166         post_code(0x06);
167
168         if (needs_reset) {
169                 print_info("ht reset -\n");
170                 soft_reset();
171         }
172
173         allow_all_aps_stop(bsp_apicid);
174
175         /* It's the time to set ctrl now; */
176         printk(BIOS_DEBUG, "sysinfo->nodes: %2x  sysinfo->ctrl: %p  spd_addr: %p\n",
177                      sysinfo->nodes, sysinfo->ctrl, spd_addr);
178         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
179
180         post_code(0x07);
181
182         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
183
184         post_code(0x08);
185
186         rs690_before_pci_init();
187         sb600_before_pci_init();
188
189         post_cache_as_ram();
190 }