2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
21 #include <arch/smp/mpspec.h>
22 #include <device/pci.h>
27 #include <cpu/amd/amdk8_sysconf.h>
30 extern u8 bus_rs690[8];
31 extern u8 bus_sb600[2];
33 extern u32 apicid_sb600;
35 extern u32 bus_type[256];
36 extern u32 sbdn_rs690;
37 extern u32 sbdn_sb600;
41 static void *smp_write_config_table(void *v)
43 static const char sig[4] = "PCMP";
44 static const char oem[8] = "COREBOOT";
45 static const char productid[12] = "PISTACHIO ";
46 struct mp_config_table *mc;
49 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
50 memset(mc, 0, sizeof(*mc));
52 memcpy(mc->mpc_signature, sig, sizeof(sig));
53 mc->mpc_length = sizeof(*mc); /* initially just the header */
55 mc->mpc_checksum = 0; /* not yet computed */
56 memcpy(mc->mpc_oem, oem, sizeof(oem));
57 memcpy(mc->mpc_productid, productid, sizeof(productid));
60 mc->mpc_entry_count = 0; /* No entries yet... */
61 mc->mpc_lapic = LAPIC_ADDR;
66 smp_write_processors(mc);
70 /* Bus: Bus ID Type */
71 /* define bus and isa numbers */
72 for (j = 0; j < bus_isa; j++) {
73 smp_write_bus(mc, j, (char *)"PCI ");
75 smp_write_bus(mc, bus_isa, (char *)"ISA ");
77 /* I/O APICs: APIC ID Version State Address */
84 dev_find_slot(bus_sb600[0],
85 PCI_DEVFN(sbdn_sb600 + 0x14, 0));
87 dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
88 smp_write_ioapic(mc, apicid_sb600, 0x11, dword);
90 /* Initialize interrupt mapping */
92 byte = pci_read_config8(dev, 0x63);
94 byte |= 0; /* 0: INTA, ...., 7: INTH */
95 pci_write_config8(dev, 0x63, byte);
98 dword = pci_read_config32(dev, 0xac);
100 dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
101 /* dword |= 1<<22; PIC and APIC co exists */
102 pci_write_config32(dev, 0xac, dword);
105 * 00:12.0: PROG SATA : INT F
106 * 00:13.0: INTA USB_0
107 * 00:13.1: INTB USB_1
108 * 00:13.2: INTC USB_2
109 * 00:13.3: INTD USB_3
110 * 00:13.4: INTC USB_4
113 * 00:14.2: Prog HDA : INT E
120 /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
121 #define IO_LOCAL_INT(type, intr, apicid, pin) \
122 smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
124 mptable_add_isa_interrupts(mc, bus_isa, apicid_sb600, 0);
126 /* PCI interrupts are level triggered, and are
127 * associated with a specific bus/device/function tuple.
129 #if CONFIG_GENERATE_ACPI_TABLES == 0
130 #define PCI_INT(bus, dev, fn, pin) \
131 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin))
133 #define PCI_INT(bus, dev, fn, pin)
137 PCI_INT(0x0, 0x13, 0x0, 0x10);
138 PCI_INT(0x0, 0x13, 0x1, 0x11);
139 PCI_INT(0x0, 0x13, 0x2, 0x12);
140 PCI_INT(0x0, 0x13, 0x3, 0x13);
143 PCI_INT(0x0, 0x12, 0x0, 0x16);
145 /* HD Audio: b0:d20:f1:reg63 should be 0. */
146 PCI_INT(0x0, 0x14, 0x0, 0x10);
148 /* on board NIC & Slot PCIE. */
149 PCI_INT(bus_rs690[1], 0x5, 0x0, 0x12);
150 PCI_INT(bus_rs690[1], 0x5, 0x1, 0x13);
151 PCI_INT(bus_rs690[2], 0x0, 0x0, 0x12);
152 PCI_INT(bus_rs690[3], 0x0, 0x0, 0x13);
153 PCI_INT(bus_rs690[4], 0x0, 0x0, 0x10);
154 PCI_INT(bus_rs690[5], 0x0, 0x0, 0x11);
155 PCI_INT(bus_rs690[6], 0x0, 0x0, 0x12);
156 PCI_INT(bus_rs690[7], 0x0, 0x0, 0x13);
160 PCI_INT(bus_sb600[1], 0x5, 0x0, 0x14);
161 PCI_INT(bus_sb600[1], 0x5, 0x1, 0x15);
162 PCI_INT(bus_sb600[1], 0x5, 0x2, 0x16);
163 PCI_INT(bus_sb600[1], 0x5, 0x3, 0x17);
166 PCI_INT(bus_sb600[1], 0x6, 0x0, 0x15);
167 PCI_INT(bus_sb600[1], 0x6, 0x1, 0x16);
168 PCI_INT(bus_sb600[1], 0x6, 0x2, 0x17);
169 PCI_INT(bus_sb600[1], 0x6, 0x3, 0x14);
172 PCI_INT(bus_sb600[1], 0x7, 0x0, 0x16);
173 PCI_INT(bus_sb600[1], 0x7, 0x1, 0x17);
174 PCI_INT(bus_sb600[1], 0x7, 0x2, 0x14);
175 PCI_INT(bus_sb600[1], 0x7, 0x3, 0x15);
177 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
178 IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
179 IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
180 /* There is no extension information... */
182 /* Compute the checksums */
184 smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
185 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
186 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
187 mc, smp_next_mpe_entry(mc));
188 return smp_next_mpe_entry(mc);
191 unsigned long write_smp_table(unsigned long addr)
194 v = smp_write_floating_table(addr);
195 return (unsigned long)smp_write_config_table(v);