2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 /* DefinitionBlock Statement */
22 "DSDT.AML", /* Output filename */
23 "DSDT", /* Signature */
24 0x02, /* DSDT Revision, needs to be 2 for 64bit */
26 "PISTACHI", /* TABLE ID */
27 0x00010001 /* OEM Revision */
29 { /* Start of ASL file */
30 /* #include "acpi/debug.asl" */ /* Include global debug methods if needed */
32 /* Data to be patched by the BIOS during POST */
33 /* FIXME the patching is not done yet! */
34 /* Memory related values */
35 Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
36 Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
37 Name(PBLN, 0x0) /* Length of BIOS area */
39 Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
40 Name(HPBA, 0xFED00000) /* Base address of HPET table */
42 Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
44 /* USB overcurrent mapping pins. */
56 /* Some global data */
57 Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
58 Name(OSV, Ones) /* Assume nothing */
59 Name(PMOD, One) /* Assume APIC */
61 /* PIC IRQ mapping registers, C00h-C01h */
62 OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
63 Field(PRQM, ByteAcc, NoLock, Preserve) {
65 PRQD, 0x00000008, /* Offset: 1h */
67 IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
68 PINA, 0x00000008, /* Index 0 */
69 PINB, 0x00000008, /* Index 1 */
70 PINC, 0x00000008, /* Index 2 */
71 PIND, 0x00000008, /* Index 3 */
72 AINT, 0x00000008, /* Index 4 */
73 SINT, 0x00000008, /* Index 5 */
74 , 0x00000008, /* Index 6 */
75 AAUD, 0x00000008, /* Index 7 */
76 AMOD, 0x00000008, /* Index 8 */
77 PINE, 0x00000008, /* Index 9 */
78 PINF, 0x00000008, /* Index A */
79 PING, 0x00000008, /* Index B */
80 PINH, 0x00000008, /* Index C */
83 /* PCI Error control register */
84 OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
85 Field(PERC, ByteAcc, NoLock, Preserve) {
92 /* Client Management index/data registers */
93 OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
94 Field(CMT, ByteAcc, NoLock, Preserve) {
96 /* Client Management Data register */
104 /* GPM Port register */
105 OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
106 Field(GPT, ByteAcc, NoLock, Preserve) {
117 /* Flash ROM program enable register */
118 OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
119 Field(FRE, ByteAcc, NoLock, Preserve) {
124 /* PM2 index/data registers */
125 OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
126 Field(PM2R, ByteAcc, NoLock, Preserve) {
131 /* Power Management I/O registers */
132 OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
133 Field(PIOR, ByteAcc, NoLock, Preserve) {
137 IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
138 Offset(0x00), /* MiscControl */
142 Offset(0x01), /* MiscStatus */
146 Offset(0x04), /* SmiWakeUpEventEnable3 */
149 Offset(0x07), /* SmiWakeUpEventStatus3 */
152 Offset(0x10), /* AcpiEnable */
155 Offset(0x1C), /* ProgramIoEnable */
162 Offset(0x1D), /* IOMonitorStatus */
169 Offset(0x20), /* AcpiPmEvtBlk */
171 Offset(0x36), /* GEvtLevelConfig */
175 Offset(0x37), /* GPMLevelConfig0 */
182 Offset(0x38), /* GPMLevelConfig1 */
189 Offset(0x3B), /* PMEStatus1 */
198 Offset(0x55), /* SoftPciRst */
206 /* Offset(0x61), */ /* Options_1 */
210 Offset(0x65), /* UsbPMControl */
213 Offset(0x68), /* MiscEnable68 */
217 Offset(0x92), /* GEVENTIN */
220 Offset(0x96), /* GPM98IN */
223 Offset(0x9A), /* EnhanceControl */
226 Offset(0xA8), /* PIO7654Enable */
231 Offset(0xA9), /* PIO7654Status */
239 * First word is PM1_Status, Second word is PM1_Enable
241 OperationRegion(P1EB, SystemIO, APEB, 0x04)
242 Field(P1EB, ByteAcc, NoLock, Preserve) {
268 /* PCIe Configuration Space for 16 busses */
269 OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
270 Field(PCFG, ByteAcc, NoLock, Preserve) {
271 /* Byte offsets are computed using the following technique:
272 * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
273 * The 8 comes from 8 functions per device, and 4096 bytes per function config space
275 Offset(0x00090024), /* Byte offset to SATA register 24h - Bus 0, Device 18, Function 0 */
277 Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
288 Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
291 Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
293 Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
295 Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
297 P92E, 1, /* Port92 decode enable */
300 OperationRegion(SB5, SystemMemory, STB5, 0x1000)
301 Field(SB5, AnyAcc, NoLock, Preserve)
304 Offset(0x120), /* Port 0 Task file status */
310 Offset(0x128), /* Port 0 Serial ATA status */
314 Offset(0x12C), /* Port 0 Serial ATA control */
316 Offset(0x130), /* Port 0 Serial ATA error */
321 offset(0x1A0), /* Port 1 Task file status */
327 Offset(0x1A8), /* Port 1 Serial ATA status */
331 Offset(0x1AC), /* Port 1 Serial ATA control */
333 Offset(0x1B0), /* Port 1 Serial ATA error */
338 Offset(0x220), /* Port 2 Task file status */
344 Offset(0x228), /* Port 2 Serial ATA status */
348 Offset(0x22C), /* Port 2 Serial ATA control */
350 Offset(0x230), /* Port 2 Serial ATA error */
355 Offset(0x2A0), /* Port 3 Task file status */
361 Offset(0x2A8), /* Port 3 Serial ATA status */
365 Offset(0x2AC), /* Port 3 Serial ATA control */
367 Offset(0x2B0), /* Port 3 Serial ATA error */
373 #include "acpi/routing.asl"
379 if(LNotEqual(OSTP, Ones)) {Return(OSTP)} /* OS version was already detected */
381 if(CondRefOf(\_OSI,Local1))
383 Store(1, OSTP) /* Assume some form of XP */
384 if (\_OSI("Windows 2006")) /* Vista */
389 If(WCMP(\_OS,"Linux")) {
390 Store(3, OSTP) /* Linux */
392 Store(4, OSTP) /* Gotta be WinCE */
398 Method(_PIC, 0x01, NotSerialized)
407 Method(CIRQ, 0x00, NotSerialized)
419 Name(IRQB, ResourceTemplate(){
420 IRQ(Level,ActiveLow,Shared){15}
423 Name(IRQP, ResourceTemplate(){
424 IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
427 Name(PITF, ResourceTemplate(){
428 IRQ(Level,ActiveLow,Exclusive){9}
432 Name(_HID, EISAID("PNP0C0F"))
437 Return(0x0B) /* sata is invisible */
439 Return(0x09) /* sata is disabled */
441 } /* End Method(_SB.INTA._STA) */
444 /* DBGO("\\_SB\\LNKA\\_DIS\n") */
446 } /* End Method(_SB.INTA._DIS) */
449 /* DBGO("\\_SB\\LNKA\\_PRS\n") */
451 } /* Method(_SB.INTA._PRS) */
454 /* DBGO("\\_SB\\LNKA\\_CRS\n") */
455 CreateWordField(IRQB, 0x1, IRQN)
456 ShiftLeft(1, PINA, IRQN)
458 } /* Method(_SB.INTA._CRS) */
461 /* DBGO("\\_SB\\LNKA\\_CRS\n") */
462 CreateWordField(ARG0, 1, IRQM)
464 /* Use lowest available IRQ */
465 FindSetRightBit(IRQM, Local0)
470 } /* End Method(_SB.INTA._SRS) */
471 } /* End Device(INTA) */
474 Name(_HID, EISAID("PNP0C0F"))
479 Return(0x0B) /* sata is invisible */
481 Return(0x09) /* sata is disabled */
483 } /* End Method(_SB.INTB._STA) */
486 /* DBGO("\\_SB\\LNKB\\_DIS\n") */
488 } /* End Method(_SB.INTB._DIS) */
491 /* DBGO("\\_SB\\LNKB\\_PRS\n") */
493 } /* Method(_SB.INTB._PRS) */
496 /* DBGO("\\_SB\\LNKB\\_CRS\n") */
497 CreateWordField(IRQB, 0x1, IRQN)
498 ShiftLeft(1, PINB, IRQN)
500 } /* Method(_SB.INTB._CRS) */
503 /* DBGO("\\_SB\\LNKB\\_CRS\n") */
504 CreateWordField(ARG0, 1, IRQM)
506 /* Use lowest available IRQ */
507 FindSetRightBit(IRQM, Local0)
512 } /* End Method(_SB.INTB._SRS) */
513 } /* End Device(INTB) */
516 Name(_HID, EISAID("PNP0C0F"))
521 Return(0x0B) /* sata is invisible */
523 Return(0x09) /* sata is disabled */
525 } /* End Method(_SB.INTC._STA) */
528 /* DBGO("\\_SB\\LNKC\\_DIS\n") */
530 } /* End Method(_SB.INTC._DIS) */
533 /* DBGO("\\_SB\\LNKC\\_PRS\n") */
535 } /* Method(_SB.INTC._PRS) */
538 /* DBGO("\\_SB\\LNKC\\_CRS\n") */
539 CreateWordField(IRQB, 0x1, IRQN)
540 ShiftLeft(1, PINC, IRQN)
542 } /* Method(_SB.INTC._CRS) */
545 /* DBGO("\\_SB\\LNKC\\_CRS\n") */
546 CreateWordField(ARG0, 1, IRQM)
548 /* Use lowest available IRQ */
549 FindSetRightBit(IRQM, Local0)
554 } /* End Method(_SB.INTC._SRS) */
555 } /* End Device(INTC) */
558 Name(_HID, EISAID("PNP0C0F"))
563 Return(0x0B) /* sata is invisible */
565 Return(0x09) /* sata is disabled */
567 } /* End Method(_SB.INTD._STA) */
570 /* DBGO("\\_SB\\LNKD\\_DIS\n") */
572 } /* End Method(_SB.INTD._DIS) */
575 /* DBGO("\\_SB\\LNKD\\_PRS\n") */
577 } /* Method(_SB.INTD._PRS) */
580 /* DBGO("\\_SB\\LNKD\\_CRS\n") */
581 CreateWordField(IRQB, 0x1, IRQN)
582 ShiftLeft(1, PIND, IRQN)
584 } /* Method(_SB.INTD._CRS) */
587 /* DBGO("\\_SB\\LNKD\\_CRS\n") */
588 CreateWordField(ARG0, 1, IRQM)
590 /* Use lowest available IRQ */
591 FindSetRightBit(IRQM, Local0)
596 } /* End Method(_SB.INTD._SRS) */
597 } /* End Device(INTD) */
600 Name(_HID, EISAID("PNP0C0F"))
605 Return(0x0B) /* sata is invisible */
607 Return(0x09) /* sata is disabled */
609 } /* End Method(_SB.INTE._STA) */
612 /* DBGO("\\_SB\\LNKE\\_DIS\n") */
614 } /* End Method(_SB.INTE._DIS) */
617 /* DBGO("\\_SB\\LNKE\\_PRS\n") */
619 } /* Method(_SB.INTE._PRS) */
622 /* DBGO("\\_SB\\LNKE\\_CRS\n") */
623 CreateWordField(IRQB, 0x1, IRQN)
624 ShiftLeft(1, PINE, IRQN)
626 } /* Method(_SB.INTE._CRS) */
629 /* DBGO("\\_SB\\LNKE\\_CRS\n") */
630 CreateWordField(ARG0, 1, IRQM)
632 /* Use lowest available IRQ */
633 FindSetRightBit(IRQM, Local0)
638 } /* End Method(_SB.INTE._SRS) */
639 } /* End Device(INTE) */
642 Name(_HID, EISAID("PNP0C0F"))
647 Return(0x0B) /* sata is invisible */
649 Return(0x09) /* sata is disabled */
651 } /* End Method(_SB.INTF._STA) */
654 /* DBGO("\\_SB\\LNKF\\_DIS\n") */
656 } /* End Method(_SB.INTF._DIS) */
659 /* DBGO("\\_SB\\LNKF\\_PRS\n") */
661 } /* Method(_SB.INTF._PRS) */
664 /* DBGO("\\_SB\\LNKF\\_CRS\n") */
665 CreateWordField(IRQB, 0x1, IRQN)
666 ShiftLeft(1, PINF, IRQN)
668 } /* Method(_SB.INTF._CRS) */
671 /* DBGO("\\_SB\\LNKF\\_CRS\n") */
672 CreateWordField(ARG0, 1, IRQM)
674 /* Use lowest available IRQ */
675 FindSetRightBit(IRQM, Local0)
680 } /* End Method(_SB.INTF._SRS) */
681 } /* End Device(INTF) */
684 Name(_HID, EISAID("PNP0C0F"))
689 Return(0x0B) /* sata is invisible */
691 Return(0x09) /* sata is disabled */
693 } /* End Method(_SB.INTG._STA) */
696 /* DBGO("\\_SB\\LNKG\\_DIS\n") */
698 } /* End Method(_SB.INTG._DIS) */
701 /* DBGO("\\_SB\\LNKG\\_PRS\n") */
703 } /* Method(_SB.INTG._CRS) */
706 /* DBGO("\\_SB\\LNKG\\_CRS\n") */
707 CreateWordField(IRQB, 0x1, IRQN)
708 ShiftLeft(1, PING, IRQN)
710 } /* Method(_SB.INTG._CRS) */
713 /* DBGO("\\_SB\\LNKG\\_CRS\n") */
714 CreateWordField(ARG0, 1, IRQM)
716 /* Use lowest available IRQ */
717 FindSetRightBit(IRQM, Local0)
722 } /* End Method(_SB.INTG._SRS) */
723 } /* End Device(INTG) */
726 Name(_HID, EISAID("PNP0C0F"))
731 Return(0x0B) /* sata is invisible */
733 Return(0x09) /* sata is disabled */
735 } /* End Method(_SB.INTH._STA) */
738 /* DBGO("\\_SB\\LNKH\\_DIS\n") */
740 } /* End Method(_SB.INTH._DIS) */
743 /* DBGO("\\_SB\\LNKH\\_PRS\n") */
745 } /* Method(_SB.INTH._CRS) */
748 /* DBGO("\\_SB\\LNKH\\_CRS\n") */
749 CreateWordField(IRQB, 0x1, IRQN)
750 ShiftLeft(1, PINH, IRQN)
752 } /* Method(_SB.INTH._CRS) */
755 /* DBGO("\\_SB\\LNKH\\_CRS\n") */
756 CreateWordField(ARG0, 1, IRQM)
758 /* Use lowest available IRQ */
759 FindSetRightBit(IRQM, Local0)
764 } /* End Method(_SB.INTH._SRS) */
765 } /* End Device(INTH) */
767 } /* End Scope(_SB) */
770 /* Supported sleep states: */
771 Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
773 If (LAnd(SSFG, 0x01)) {
774 Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
776 If (LAnd(SSFG, 0x02)) {
777 Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
779 If (LAnd(SSFG, 0x04)) {
780 Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
782 If (LAnd(SSFG, 0x08)) {
783 Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
786 Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
788 Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
789 Name(CSMS, 0) /* Current System State */
791 /* Wake status package */
792 Name(WKST,Package(){Zero, Zero})
795 * \_PTS - Prepare to Sleep method
798 * Arg0=The value of the sleeping state S1=1, S2=2, etc
803 * The _PTS control method is executed at the beginning of the sleep process
804 * for S1-S5. The sleeping value is passed to the _PTS control method. This
805 * control method may be executed a relatively long time before entering the
806 * sleep state and the OS may abort the operation without notification to
807 * the ACPI driver. This method cannot modify the configuration or power
808 * state of any device in the system.
811 /* DBGO("\\_PTS\n") */
812 /* DBGO("From S0 to S") */
816 /* Don't allow PCIRST# to reset USB */
821 /* Clear sleep SMI status flag and enable sleep SMI trap. */
825 /* On older chips, clear PciExpWakeDisEn */
826 /*if (LLessEqual(\_SB.SBRI, 0x13)) {
831 /* Clear wake status structure. */
832 Store(0, Index(WKST,0))
833 Store(0, Index(WKST,1))
834 } /* End Method(\_PTS) */
837 * The following method results in a "not a valid reserved NameSeg"
838 * warning so I have commented it out for the duration. It isn't
839 * used, so it could be removed.
842 * \_GTS OEM Going To Sleep method
845 * Arg0=The value of the sleeping state S1=1, S2=2
852 * DBGO("From S0 to S")
859 * \_BFS OEM Back From Sleep method
862 * Arg0=The value of the sleeping state S1=1, S2=2
868 /* DBGO("\\_BFS\n") */
871 /* DBGO(" to S0\n") */
875 * \_WAK System Wake method
878 * Arg0=The value of the sleeping state S1=1, S2=2
881 * Return package of 2 DWords
883 * 0x00000000 wake succeeded
884 * 0x00000001 Wake was signaled but failed due to lack of power
885 * 0x00000002 Wake was signaled but failed due to thermal condition
886 * Dword 2 - Power Supply state
887 * if non-zero the effective S-state the power supply entered
890 /* DBGO("\\_WAK\n") */
893 /* DBGO(" to S0\n") */
898 /* Restore PCIRST# so it resets USB */
903 /* Arbitrarily clear PciExpWakeStatus */
906 /* if(DeRefOf(Index(WKST,0))) {
907 * Store(0, Index(WKST,1))
909 * Store(Arg0, Index(WKST,1))
914 } /* End Method(\_WAK) */
916 Scope(\_GPE) { /* Start Scope GPE */
917 /* General event 0 */
919 * DBGO("\\_GPE\\_L00\n")
923 /* General event 1 */
925 * DBGO("\\_GPE\\_L00\n")
929 /* General event 2 */
931 * DBGO("\\_GPE\\_L00\n")
935 /* General event 3 */
937 /* DBGO("\\_GPE\\_L00\n") */
938 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
941 /* General event 4 */
943 * DBGO("\\_GPE\\_L00\n")
947 /* General event 5 */
949 * DBGO("\\_GPE\\_L00\n")
953 /* General event 6 - Used for GPM6, moved to USB.asl */
955 * DBGO("\\_GPE\\_L00\n")
959 /* General event 7 - Used for GPM7, moved to USB.asl */
961 * DBGO("\\_GPE\\_L07\n")
965 /* Legacy PM event */
967 /* DBGO("\\_GPE\\_L08\n") */
970 /* Temp warning (TWarn) event */
972 /* DBGO("\\_GPE\\_L09\n") */
973 Notify (\_TZ.TZ00, 0x80)
978 * DBGO("\\_GPE\\_L0A\n")
982 /* USB controller PME# */
984 /* DBGO("\\_GPE\\_L0B\n") */
985 Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
986 Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
987 Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
988 Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
989 Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
990 Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
991 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
994 /* AC97 controller PME# */
996 * DBGO("\\_GPE\\_L0C\n")
1000 /* OtherTherm PME# */
1002 * DBGO("\\_GPE\\_L0D\n")
1006 /* GPM9 SCI event - Moved to USB.asl */
1008 * DBGO("\\_GPE\\_L0E\n")
1012 /* PCIe HotPlug event */
1014 * DBGO("\\_GPE\\_L0F\n")
1018 /* ExtEvent0 SCI event */
1020 /* DBGO("\\_GPE\\_L10\n") */
1024 /* ExtEvent1 SCI event */
1026 /* DBGO("\\_GPE\\_L11\n") */
1029 /* PCIe PME# event */
1031 * DBGO("\\_GPE\\_L12\n")
1035 /* GPM0 SCI event - Moved to USB.asl */
1037 * DBGO("\\_GPE\\_L13\n")
1041 /* GPM1 SCI event - Moved to USB.asl */
1043 * DBGO("\\_GPE\\_L14\n")
1047 /* GPM2 SCI event - Moved to USB.asl */
1049 * DBGO("\\_GPE\\_L15\n")
1053 /* GPM3 SCI event - Moved to USB.asl */
1055 * DBGO("\\_GPE\\_L16\n")
1059 /* GPM8 SCI event - Moved to USB.asl */
1061 * DBGO("\\_GPE\\_L17\n")
1065 /* GPIO0 or GEvent8 event */
1067 /* DBGO("\\_GPE\\_L18\n") */
1068 Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
1069 Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
1070 Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
1071 Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
1072 Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
1073 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1076 /* GPM4 SCI event - Moved to USB.asl */
1078 * DBGO("\\_GPE\\_L19\n")
1082 /* GPM5 SCI event */
1084 /* DBGO("\\_GPE\\_L1A\n") */
1085 Notify (\_SB.SLPB, 0x80)
1088 /* Azalia SCI event */
1090 /* DBGO("\\_GPE\\_L1B\n") */
1091 Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
1092 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1095 /* GPM6 SCI event - Reassigned to _L06 */
1097 * DBGO("\\_GPE\\_L1C\n")
1101 /* GPM7 SCI event - Reassigned to _L07 */
1103 * DBGO("\\_GPE\\_L1D\n")
1107 /* GPIO2 or GPIO66 SCI event */
1109 * DBGO("\\_GPE\\_L1E\n")
1113 /* SATA SCI event - Moved to sata.asl */
1115 * DBGO("\\_GPE\\_L1F\n")
1119 } /* End Scope GPE */
1121 #include "acpi/usb.asl"
1124 Scope(\_SB) { /* Start \_SB scope */
1125 #include "acpi/globutil.asl" /* global utility methods expected within the \_SB scope */
1128 /* Note: Only need HID on Primary Bus */
1131 External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
1132 Name(_HID, EISAID("PNP0A03"))
1133 Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
1134 Method(_BBN, 0) { /* Bus number = 0 */
1138 /* DBGO("\\_SB\\PCI0\\_STA\n") */
1139 Return(0x0B) /* Status is visible */
1143 If(PMOD){ Return(APR0) } /* APIC mode */
1144 Return (PR0) /* PIC Mode */
1147 /* Describe the Northbridge devices */
1149 Name(_ADR, 0x00000000)
1152 /* The internal GFX bridge */
1154 Name(_ADR, 0x00010000)
1155 Name(_PRW, Package() {0x18, 4})
1161 /* The external GFX bridge */
1163 Name(_ADR, 0x00020000)
1164 Name(_PRW, Package() {0x18, 4})
1166 If(PMOD){ Return(APS2) } /* APIC mode */
1167 Return (PS2) /* PIC Mode */
1171 /* Dev3 is also an external GFX bridge, not used in Herring */
1174 Name(_ADR, 0x00040000)
1175 Name(_PRW, Package() {0x18, 4})
1177 If(PMOD){ Return(APS4) } /* APIC mode */
1178 Return (PS4) /* PIC Mode */
1183 Name(_ADR, 0x00050000)
1184 Name(_PRW, Package() {0x18, 4})
1186 If(PMOD){ Return(APS5) } /* APIC mode */
1187 Return (PS5) /* PIC Mode */
1192 Name(_ADR, 0x00060000)
1193 Name(_PRW, Package() {0x18, 4})
1195 If(PMOD){ Return(APS6) } /* APIC mode */
1196 Return (PS6) /* PIC Mode */
1200 /* The onboard EtherNet chip */
1202 Name(_ADR, 0x00070000)
1203 Name(_PRW, Package() {0x18, 4})
1205 If(PMOD){ Return(APS7) } /* APIC mode */
1206 Return (PS7) /* PIC Mode */
1211 /* PCI slot 1, 2, 3 */
1213 Name(_ADR, 0x00140004)
1214 Name(_PRW, Package() {0x18, 4})
1221 /* Describe the Southbridge devices */
1223 Name(_ADR, 0x00120000)
1224 #include "acpi/sata.asl"
1228 Name(_ADR, 0x00130000)
1229 Name(_PRW, Package() {0x0B, 3})
1233 Name(_ADR, 0x00130001)
1234 Name(_PRW, Package() {0x0B, 3})
1238 Name(_ADR, 0x00130002)
1239 Name(_PRW, Package() {0x0B, 3})
1243 Name(_ADR, 0x00130003)
1244 Name(_PRW, Package() {0x0B, 3})
1248 Name(_ADR, 0x00130004)
1249 Name(_PRW, Package() {0x0B, 3})
1253 Name(_ADR, 0x00130005)
1254 Name(_PRW, Package() {0x0B, 3})
1258 Name(_ADR, 0x00140000)
1261 /* Primary (and only) IDE channel */
1263 Name(_ADR, 0x00140001)
1264 #include "acpi/ide.asl"
1268 Name(_ADR, 0x00140002)
1269 OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
1270 Field(AZPD, AnyAcc, NoLock, Preserve) {
1294 If(LEqual(OSTP,3)){ /* If we are running Linux */
1303 Name(_ADR, 0x00140003)
1305 * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
1306 } */ /* End Method(_SB.SBRDG._INI) */
1308 /* Real Time Clock Device */
1310 Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */
1311 Name(_CRS, ResourceTemplate() {
1313 IO(Decode16,0x0070, 0x0070, 0, 2)
1314 /* IO(Decode16,0x0070, 0x0070, 0, 4) */
1316 } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
1318 Device(TMR) { /* Timer */
1319 Name(_HID,EISAID("PNP0100")) /* System Timer */
1320 Name(_CRS, ResourceTemplate() {
1322 IO(Decode16, 0x0040, 0x0040, 0, 4)
1323 /* IO(Decode16, 0x0048, 0x0048, 0, 4) */
1325 } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
1327 Device(SPKR) { /* Speaker */
1328 Name(_HID,EISAID("PNP0800")) /* AT style speaker */
1329 Name(_CRS, ResourceTemplate() {
1330 IO(Decode16, 0x0061, 0x0061, 0, 1)
1332 } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
1335 Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */
1336 Name(_CRS, ResourceTemplate() {
1338 IO(Decode16,0x0020, 0x0020, 0, 2)
1339 IO(Decode16,0x00A0, 0x00A0, 0, 2)
1340 /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
1341 /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
1343 } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
1345 Device(MAD) { /* 8257 DMA */
1346 Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */
1347 Name(_CRS, ResourceTemplate() {
1348 DMA(Compatibility,BusMaster,Transfer8){4}
1349 IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
1350 IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
1351 IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
1352 IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
1353 IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
1354 IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
1355 }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
1356 } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
1359 Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
1360 Name(_CRS, ResourceTemplate() {
1361 IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
1364 } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
1367 Name(_HID,EISAID("PNP0103"))
1368 Name(CRS,ResourceTemplate() {
1369 Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
1372 Return(0x0F) /* sata is visible */
1375 CreateDwordField(CRS, ^HPT._BAS, HPBA)
1379 } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
1383 Name(_ADR, 0x00140004)
1384 } /* end HostPciBr */
1387 Name(_ADR, 0x00140005)
1388 } /* end Ac97audio */
1391 Name(_ADR, 0x00140006)
1392 } /* end Ac97modem */
1394 Name(CRES, ResourceTemplate() {
1395 IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
1397 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1398 0x0000, /* address granularity */
1399 0x0000, /* range minimum */
1400 0x0CF7, /* range maximum */
1401 0x0000, /* translation */
1405 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1406 0x0000, /* address granularity */
1407 0x0D00, /* range minimum */
1408 0xFFFF, /* range maximum */
1409 0x0000, /* translation */
1413 Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
1414 Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
1415 Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
1416 Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */
1418 /* DRAM Memory from 1MB to TopMem */
1419 Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */
1421 /* BIOS space just below 4GB */
1423 ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1424 0x00, /* Granularity */
1425 0x00000000, /* Min */
1426 0x00000000, /* Max */
1427 0x00000000, /* Translation */
1428 0x00000001, /* Max-Min, RLEN */
1433 /* DRAM memory from 4GB to TopMem2 */
1434 QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1435 0x00000000, /* Granularity */
1436 0x00000000, /* Min */
1437 0x00000000, /* Max */
1438 0x00000000, /* Translation */
1439 0x00000001, /* Max-Min, RLEN */
1444 /* BIOS space just below 16EB */
1445 QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1446 0x00000000, /* Granularity */
1447 0x00000000, /* Min */
1448 0x00000000, /* Max */
1449 0x00000000, /* Translation */
1450 0x00000001, /* Max-Min, RLEN */
1455 }) /* End Name(_SB.PCI0.CRES) */
1458 /* DBGO("\\_SB\\PCI0\\_CRS\n") */
1460 CreateDWordField(CRES, ^EMM1._BAS, EM1B)
1461 CreateDWordField(CRES, ^EMM1._LEN, EM1L)
1462 CreateDWordField(CRES, ^DMLO._BAS, DMLB)
1463 CreateDWordField(CRES, ^DMLO._LEN, DMLL)
1464 CreateDWordField(CRES, ^PCBM._MIN, PBMB)
1465 CreateDWordField(CRES, ^PCBM._LEN, PBML)
1467 CreateQWordField(CRES, ^DMHI._MIN, DMHB)
1468 CreateQWordField(CRES, ^DMHI._LEN, DMHL)
1469 CreateQWordField(CRES, ^PEBM._MIN, EBMB)
1470 CreateQWordField(CRES, ^PEBM._LEN, EBML)
1472 If(LGreater(LOMH, 0xC0000)){
1473 Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */
1474 Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */
1477 /* Set size of memory from 1MB to TopMem */
1478 Subtract(TOM1, 0x100000, DMLL)
1481 * If(LNotEqual(TOM2, 0x00000000)){
1482 * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2
1483 * ShiftLeft(TOM2, 20, Local0)
1484 * Subtract(Local0, 0x100000000, DMHL)
1488 /* If there is no memory above 4GB, put the BIOS just below 4GB */
1489 If(LEqual(TOM2, 0x00000000)){
1490 Store(PBAD,PBMB) /* Reserve the "BIOS" space */
1493 Else { /* Otherwise, put the BIOS just below 16EB */
1494 ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */
1498 Return(CRES) /* note to change the Name buffer */
1499 } /* end of Method(_SB.PCI0._CRS) */
1503 * FIRST METHOD CALLED UPON BOOT
1505 * 1. If debugging, print current OS and ACPI interpreter.
1506 * 2. Get PCI Interrupt routing from ACPI VSM, this
1507 * value is based on user choice in BIOS setup.
1510 /* DBGO("\\_SB\\_INI\n") */
1511 /* DBGO(" DSDT.ASL code from ") */
1512 /* DBGO(__DATE__) */
1514 /* DBGO(__TIME__) */
1515 /* DBGO("\n Sleep states supported: ") */
1517 /* DBGO(" \\_OS=") */
1519 /* DBGO("\n \\_REV=") */
1523 /* Determine the OS we're running on */
1526 /* On older chips, clear PciExpWakeDisEn */
1527 /*if (LLessEqual(\SBRI, 0x13)) {
1531 } /* End Method(_SB._INI) */
1532 } /* End Device(PCI0) */
1534 Device(PWRB) { /* Start Power button device */
1535 Name(_HID, EISAID("PNP0C0C"))
1537 Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */
1538 Name(_STA, 0x0B) /* sata is invisible */
1542 Name (_HID, EisaId ("PNP0C0E"))
1543 Name (_PRW, Package (0x02) {0x0F, 0x04})
1546 } /* End \_SB scope */
1550 /* DBGO("\\_SI\\_SST\n") */
1551 /* DBGO(" New Indicator state: ") */
1555 } /* End Scope SI */
1557 OperationRegion (SMB0, SystemIO, 0xB00, 0x0C)
1558 Field (SMB0, ByteAcc, NoLock, Preserve) {
1559 HSTS, 8, /* SMBUS status */
1560 SSTS, 8, /* SMBUS slave status */
1561 HCNT, 8, /* SMBUS control */
1562 HCMD, 8, /* SMBUS host cmd */
1563 HADD, 8, /* SMBUS address */
1564 DAT0, 8, /* SMBUS data0 */
1565 DAT1, 8, /* SMBUS data1 */
1566 BLKD, 8, /* SMBUS block data */
1567 SCNT, 8, /* SMBUS slave control */
1568 SCMD, 8, /* SMBUS shaow cmd */
1569 SEVT, 8, /* SMBUS slave event */
1570 SDAT, 8 /* SMBUS slave data */
1573 Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */
1575 Store (0xFA, Local0)
1576 While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) {
1584 Method (SWTC, 1, NotSerialized) {
1585 Store (Arg0, Local0)
1586 Store (0x07, Local2)
1588 While (LEqual (Local1, One)) {
1589 Store (And (HSTS, 0x1E), Local3)
1590 If (LNotEqual (Local3, Zero)) { /* read sucess */
1591 If (LEqual (Local3, 0x02)) {
1592 Store (Zero, Local2)
1595 Store (Zero, Local1)
1598 If (LLess (Local0, 0x0A)) { /* read failure */
1599 Store (0x18, Local2)
1600 Store (Zero, Local1)
1603 Sleep (0x0A) /* 10 ms, try again */
1604 Subtract (Local0, 0x0A, Local0)
1612 Method (SMBR, 3, NotSerialized) {
1613 Store (0x07, Local0)
1615 Store (WCLR (), Local0) /* clear SMBUS status register before read data */
1618 Store (Or (ShiftLeft (Arg1, One), One), HADD)
1620 If (LEqual (Arg0, 0x07)) {
1621 Store (0x48, HCNT) /* read byte */
1624 Store (SWTC (0x03E8), Local1) /* 1000 ms */
1625 If (LEqual (Local1, Zero)) {
1626 If (LEqual (Arg0, 0x07)) {
1627 Store (DAT0, Local0)
1631 Store (Local1, Local0)
1644 Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */
1645 /* DBGO("\\_TZ\\TZ00\\_AC0\n") */
1646 Return(Add(0, 2730))
1648 Method(_AL0,0) { /* Returns package of cooling device to turn on */
1649 /* DBGO("\\_TZ\\TZ00\\_AL0\n") */
1650 Return(Package() {\_TZ.TZ00.FAN0})
1653 Name(_HID, EISAID("PNP0C0B"))
1654 Name(_PR0, Package() {PFN0})
1657 PowerResource(PFN0,0,0) {
1663 /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
1666 /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
1670 Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */
1671 /* DBGO("\\_TZ\\TZ00\\_HOT\n") */
1672 Return (Add (THOT, KELV))
1674 Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */
1675 /* DBGO("\\_TZ\\TZ00\\_CRT\n") */
1676 Return (Add (TCRT, KELV))
1678 Method(_TMP,0) { /* return current temp of this zone */
1679 Store (SMBR (0x07, 0x2E,, 0x25), Local0)
1680 If (LGreater (Local0, 0x20)) {
1681 Store (Local0, Local1)
1684 Add (Local0, 0x40, Local0)
1685 Add (Local0, TCRT, Local0)
1686 Return (Add (550, KELV))
1689 /* Store (SMBR (0x07, 0x2E, 0x26), Local0)
1690 * If (LGreater (Local0, 0x20)) {
1691 * If (LGreater (Local0, Local1)) {
1692 * Store (Local0, Local1)
1696 * Add (Local0, 0x40, Local0)
1697 * Add (Local0, TCRT, Local0)
1698 * Return (Add (Local0, KELV))
1702 Store (SMBR (0x07, 0x2E, 0x27), Local0)
1703 If (LGreater (Local0, 0x20)) {
1704 If (LGreater (Local0, Local1)) {
1705 Store (Local0, Local1)
1708 Subtract (Local1, 0x40, Local1)
1709 Multiply (Local1, 10, Local1)
1710 Return (Add (Local1, KELV))
1713 Add (Local0, 0x40, Local0)
1714 Add (Local0, TCRT, Local0)
1715 Return (Add (550 , KELV))
1721 /* End of ASL file */