src/mainboard/amd/pistachio/acpi_tables.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 #include <console/console.h>
  21 #include <string.h>
  22 #include <arch/acpi.h>
  23 #include <device/pci.h>
  24 #include <device/pci_ids.h>
  25 #include <cpu/x86/msr.h>
  26 #include <cpu/amd/mtrr.h>
  27 #include <cpu/amd/amdk8_sysconf.h>
  28 #include <../../../northbridge/amd/amdk8/amdk8_acpi.h>
  29 #include <arch/cpu.h>
  30
  31 #define DUMP_ACPI_TABLES 0
  32
  33 /*
  34 * Assume the max pstate number is 8
  35 * 0x21(33 bytes) is one package length of _PSS package
  36 */
  37
  38 #define Maxpstate 8
  39 #define Defpkglength 0x21
  40
  41 #if DUMP_ACPI_TABLES == 1
  42 static void dump_mem(u32 start, u32 end)
  43 {
  44
  45         u32 i;
  46         print_debug("dump_mem:");
  47         for (i = start; i < end; i++) {
  48                 if ((i & 0xf) == 0) {
  49                         printk_debug("\n%08x:", i);
  50                 }
  51                 printk_debug(" %02x", (u8)*((u8 *)i));
  52         }
  53         print_debug("\n");
  54 }
  55 #endif
  56
  57 extern u8 AmlCode[];
  58
  59 #if ACPI_SSDTX_NUM >= 1
  60 extern u8 AmlCode_ssdt2[];
  61 extern u8 AmlCode_ssdt3[];
  62 extern u8 AmlCode_ssdt4[];
  63 extern u8 AmlCode_ssdt5[];
  64 #endif
  65
  66 #define IO_APIC_ADDR    0xfec00000UL
  67
  68 unsigned long acpi_fill_mcfg(unsigned long current)
  69 {
  70         /* Just a dummy */
  71         return current;
  72 }
  73
  74 unsigned long acpi_fill_madt(unsigned long current)
  75 {
  76         /* create all subtables for processors */
  77         current = acpi_create_madt_lapics(current);
  78
  79         /* Write SB600 IOAPIC, only one */
  80         current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2,
  81                                            IO_APIC_ADDR, 0);
  82
  83         current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
  84                                                 current, 0, 0, 2, 0);
  85         current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
  86                                                 current, 0, 9, 9, 0xF);
  87         /* 0: mean bus 0--->ISA */
  88         /* 0: PIC 0 */
  89         /* 2: APIC 2 */
  90         /* 5 mean: 0101 --> Edige-triggered, Active high */
  91
  92         /* create all subtables for processors */
  93         /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
  94         /* 1: LINT1 connect to NMI */
  95
  96         return current;
  97 }
  98
  99 extern void get_bus_conf(void);
 100
 101 void update_ssdtx(void *ssdtx, int i)
 102 {
 103         uint8_t *PCI;
 104         uint8_t *HCIN;
 105         uint8_t *UID;
 106
 107         PCI = ssdtx + 0x32;
 108         HCIN = ssdtx + 0x39;
 109         UID = ssdtx + 0x40;
 110
 111         if (i < 7) {
 112                 *PCI = (uint8_t) ('4' + i - 1);
 113         } else {
 114                 *PCI = (uint8_t) ('A' + i - 1 - 6);
 115         }
 116         *HCIN = (uint8_t) i;
 117         *UID = (uint8_t) (i + 3);
 118
 119         /* FIXME: need to update the GSI id in the ssdtx too */
 120
 121 }
 122
 123 /*
 124 * Details about this algorithm , refert to BDKG 10.5.1
 125 * Two parts are included, the another is the DSDT reconstruction process
 126 */
 127 u32 pstates_algorithm(acpi_header_t * dsdt)
 128 {
 129         u8 processor_brand[49];
 130         u32 *v;
 131         struct cpuid_result cpuid1;
 132
 133         struct power_limit_encoding {
 134                 u8 socket_type;
 135                 u8 cmp_cap;
 136                 u8 pwr_lmt;
 137                 u32 power_limit;
 138         };
 139         u8 Max_fid, Max_vid, Start_fid, Start_vid, Min_fid, Min_vid;
 140         u16 Max_feq;
 141         u8 Pstate_fid[10];
 142         u16 Pstate_feq[10];
 143         u8 Pstate_vid[10];
 144         u32 Pstate_power[10];
 145         u32 Pstate_volt[10];
 146         u8 PstateStep, PstateStep_coef;
 147         u8 IntPstateSup;
 148         u8 Pstate_num;
 149         u16 Cur_feq;
 150         u8 Cur_fid;
 151         u8 cmp_cap, pwr_lmt;
 152         u32 power_limit = 0;
 153         u8 index;
 154         u32 i, j;
 155         u32 processor_length, scope_length;
 156         msr_t msr;
 157         u8 *dsdt_pointer;
 158         u8 *pointer1;
 159         u8 *pointer2;
 160         u8 byte_index;
 161         u32 old_dsdt_length, new_dsdt_length;
 162         u32 corefeq, power, transitionlatency, busmasterlatency, control,
 163             status;
 164         u32 new_package_length;
 165         u8 sum, checksum;
 166         u32 fid_multiplier;
 167         static struct power_limit_encoding TDP[20] = {
 168                 {0x11, 0x0, 0x8, 62},
 169                 {0x11, 0x1, 0x8, 89},
 170                 {0x11, 0x1, 0xa, 103},
 171                 {0x11, 0x1, 0xc, 125},
 172                 {0x11, 0x0, 0x2, 15},
 173                 {0x11, 0x0, 0x4, 35},
 174                 {0x11, 0x1, 0x2, 35},
 175                 {0x11, 0x0, 0x5, 45},
 176                 {0x11, 0x1, 0x7, 76},
 177                 {0x11, 0x1, 0x6, 65},
 178                 {0x11, 0x1, 0x8, 89},
 179                 {0x11, 0x0, 0x1, 8},
 180                 {0x11, 0x1, 0x1, 22},
 181                 {0x12, 0x0, 0x6, 25},
 182                 {0x12, 0x0, 0x1, 8},
 183                 {0x12, 0x0, 0x2, 9},
 184                 {0x12, 0x0, 0x4, 15},
 185                 {0x12, 0x0, 0xc, 35},
 186                 {0x12, 0x1, 0xc, 35},
 187                 {0x12, 0x1, 0x4, 20}
 188         };
 189
 190         /* Get the Processor Brand String using cpuid(0x8000000x) command x=2,3,4 */
 191         cpuid1 = cpuid(0x80000002);
 192         v = (u32 *) processor_brand;
 193         v[0] = cpuid1.eax;
 194         v[1] = cpuid1.ebx;
 195         v[2] = cpuid1.ecx;
 196         v[3] = cpuid1.edx;
 197         cpuid1 = cpuid(0x80000003);
 198         v[4] = cpuid1.eax;
 199         v[5] = cpuid1.ebx;
 200         v[6] = cpuid1.ecx;
 201         v[7] = cpuid1.edx;
 202         cpuid1 = cpuid(0x80000004);
 203         v[8] = cpuid1.eax;
 204         v[9] = cpuid1.ebx;
 205         v[10] = cpuid1.ecx;
 206         v[11] = cpuid1.edx;
 207         processor_brand[48] = 0;
 208         printk_info("processor_brand=%s\n", processor_brand);
 209
 210         /*
 211          * Based on the CPU socket type,cmp_cap and pwr_lmt , get the power limit.
 212          * socket_type : 0x10 SocketF; 0x11 AM2/ASB1 ; 0x12 S1G1
 213          * cmp_cap : 0x0 SingleCore ; 0x1 DualCore
 214          */
 215         printk_info("Pstates Algorithm ...\n");
 216         cmp_cap =
 217             (pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xE8) &
 218              0x3000) >> 12;
 219         cpuid1 = cpuid(0x80000001);
 220         pwr_lmt = ((cpuid1.ebx & 0x1C0) >> 5) | ((cpuid1.ebx & 0x4000) >> 14);
 221         for (index = 0; index <= sizeof(TDP) / sizeof(TDP[0]); index++)
 222                 if (TDP[index].socket_type == CPU_SOCKET_TYPE &&
 223                     TDP[index].cmp_cap == cmp_cap &&
 224                     TDP[index].pwr_lmt == pwr_lmt) {
 225                         power_limit = TDP[index].power_limit;
 226                 }
 227
 228         /* See if the CPUID(0x80000007) returned EDX[2:1]==11b */
 229         cpuid1 = cpuid(0x80000007);
 230         if ((cpuid1.edx & 0x6) != 0x6) {
 231                 printk_info("No valid set of P-states\n");
 232                 return 0;
 233         }
 234
 235         msr = rdmsr(0xc0010042);
 236         Max_fid = (msr.lo & 0x3F0000) >> 16;
 237         Start_fid = (msr.lo & 0x3F00) >> 8;
 238         Max_vid = (msr.hi & 0x3F0000) >> 16;
 239         Start_vid = (msr.hi & 0x3F00) >> 8;
 240         PstateStep = (msr.hi & 0x1000000) >> 24;
 241         IntPstateSup = (msr.hi & 0x20000000) >> 29;
 242
 243         /*
 244          * The P1...P[Min+1] VID need PstateStep to calculate
 245          * P[N] = P[N-1]VID + 2^PstateStep
 246          * PstateStep_coef = 2^PstateStep
 247          */
 248         if (PstateStep == 0)
 249                 PstateStep_coef = 1;
 250         else
 251                 PstateStep_coef = 2;
 252
 253         if (IntPstateSup == 0) {
 254                 printk_info("No intermediate P-states are supported\n");
 255                 return 0;
 256         }
 257
 258         /* Get the multipier of the fid frequency */
 259         /*
 260          * Fid multiplier is always 100 revF and revG.
 261          */
 262         fid_multiplier = 100;
 263
 264         /*
 265          * Formula1:    CPUFreq = FID * fid_multiplier + 800
 266          * Formula2:       CPUVolt = 1550 - VID * 25 (mv)
 267          * Formula3:       Power = (PwrLmt * P[N]Frequency*(P[N]Voltage^2))/(P[0]Frequency * P[0]Voltage^2))
 268          */
 269
 270         /* Construct P0(P[Max]) state */
 271         Pstate_num = 0;
 272         Max_feq = Max_fid * fid_multiplier + 800;
 273         if (Max_fid == 0x2A && Max_vid != 0x0) {
 274                 Min_fid = 0x2;
 275                 Pstate_fid[0] = Start_fid + 0xA;        /* Start Frequency + 1GHz */
 276                 Pstate_feq[0] = Pstate_fid[0] * fid_multiplier + 800;
 277                 Min_vid = Start_vid;
 278                 Pstate_vid[0] = Max_vid + 0x2;  /* Maximum Voltage - 50mV */
 279                 Pstate_volt[0] = 1550 - Pstate_vid[0] * 25;
 280                 Pstate_power[0] = power_limit * 1000;   /* mw */
 281                 Pstate_num++;
 282         } else {
 283                 Min_fid = Start_fid;
 284                 Pstate_fid[0] = Max_fid;
 285                 Pstate_feq[0] = Max_feq;
 286                 Min_vid = Start_vid;
 287                 Pstate_vid[0] = Max_vid + 0x2;
 288                 Pstate_volt[0] = 1550 - Pstate_vid[0] * 25;
 289                 Pstate_power[0] = power_limit * 1000;   /* mw */
 290                 Pstate_num++;
 291         }
 292
 293         Cur_feq = Max_feq;
 294         Cur_fid = Max_fid;
 295         /* Construct P1 state */
 296         if (((Max_fid & 0x1) != 0) && ((Max_fid - 0x1) >= (Min_fid + 0x8))) {   /* odd value */
 297                 Pstate_fid[1] = Max_fid - 0x1;
 298                 Pstate_feq[1] = Pstate_fid[1] * fid_multiplier + 800;
 299                 Cur_fid = Pstate_fid[1];
 300                 Cur_feq = Pstate_feq[1];
 301                 if (((Pstate_vid[0] & 0x1) != 0) && ((Pstate_vid[0] - 0x1) < Min_vid)) {        /* odd value */
 302                         Pstate_vid[1] = Pstate_vid[0] + 0x1;
 303                         Pstate_volt[1] = 1550 - Pstate_vid[1] * 25;
 304                         Pstate_power[1] =
 305                             (unsigned long long)Pstate_power[0] *
 306                             Pstate_feq[1] * Pstate_volt[1] * Pstate_volt[1] /
 307                             (Pstate_feq[0] * Pstate_volt[0] * Pstate_volt[0]);
 308                 }
 309                 if (((Pstate_vid[0] & 0x1) == 0) && ((Pstate_vid[0] - 0x1) < Min_vid)) {        /* even value */
 310                         Pstate_vid[1] = Pstate_vid[0] + PstateStep_coef;
 311                         Pstate_volt[1] = 1550 - Pstate_vid[1] * 25;
 312                         Pstate_power[1] =
 313                             (unsigned long long)Pstate_power[0] *
 314                             Pstate_feq[1] * Pstate_volt[1] * Pstate_volt[1] /
 315                             (Pstate_feq[0] * Pstate_volt[0] * Pstate_volt[0]);
 316                 }
 317                 Pstate_num++;
 318         }
 319
 320         if (((Max_fid & 0x1) == 0) && ((Max_fid - 0x2) >= (Min_fid + 0x8))) {   /* even value */
 321                 Pstate_fid[1] = Max_fid - 0x2;
 322                 Pstate_feq[1] = Pstate_fid[1] * fid_multiplier + 800;
 323                 Cur_fid = Pstate_fid[1];
 324                 Cur_feq = Pstate_feq[1];
 325                 if (((Pstate_vid[0] & 0x1) != 0) && ((Pstate_vid[0] - 0x1) < Min_vid)) {        /* odd value */
 326                         Pstate_vid[1] = Pstate_vid[0] + 0x1;
 327                         Pstate_volt[1] = 1550 - Pstate_vid[1] * 25;
 328                         Pstate_power[1] =
 329                             (unsigned long long)Pstate_power[0] *
 330                             Pstate_feq[1] * Pstate_volt[1] * Pstate_volt[1] /
 331                             (Pstate_feq[0] * Pstate_volt[0] * Pstate_volt[0]);
 332                 }
 333                 if (((Pstate_vid[0] & 0x1) == 0) && ((Pstate_vid[0] - 0x1) < Min_vid)) {        /* even value */
 334                         Pstate_vid[1] = Pstate_vid[0] + PstateStep_coef;
 335                         Pstate_volt[1] = 1550 - Pstate_vid[1] * 25;
 336                         Pstate_power[1] =
 337                             (unsigned long long)Pstate_power[0] *
 338                             Pstate_feq[1] * Pstate_volt[1] * Pstate_volt[1] /
 339                             (Pstate_feq[0] * Pstate_volt[0] * Pstate_volt[0]);
 340                 }
 341
 342                 Pstate_num++;
 343         }
 344
 345         /* Construct P2...P[Min-1] state */
 346         Cur_fid = Cur_fid - 0x2;
 347         Cur_feq = Cur_fid * fid_multiplier + 800;
 348         while (Cur_feq >= ((Min_fid * fid_multiplier) + 800) * 2) {
 349                 Pstate_fid[Pstate_num] = Cur_fid;
 350                 Pstate_feq[Pstate_num] =
 351                     Pstate_fid[Pstate_num] * fid_multiplier + 800;
 352                 Cur_fid = Cur_fid - 0x2;
 353                 Cur_feq = Cur_fid * fid_multiplier + 800;
 354                 if (Pstate_vid[Pstate_num - 1] >= Min_vid) {
 355                         Pstate_vid[Pstate_num] = Pstate_vid[Pstate_num - 1];
 356                         Pstate_volt[Pstate_num] = Pstate_volt[Pstate_num - 1];
 357                         Pstate_power[Pstate_num] = Pstate_power[Pstate_num - 1];
 358                 } else {
 359                         Pstate_vid[Pstate_num] =
 360                             Pstate_vid[Pstate_num - 1] + PstateStep_coef;
 361                         Pstate_volt[Pstate_num] =
 362                             1550 - Pstate_vid[Pstate_num] * 25;
 363                         Pstate_power[Pstate_num] =
 364                             (unsigned long long)Pstate_power[0] *
 365                             Pstate_feq[Pstate_num] * Pstate_volt[Pstate_num] *
 366                             Pstate_volt[Pstate_num] / (Pstate_feq[0] *
 367                                                        Pstate_volt[0] *
 368                                                        Pstate_volt[0]);
 369                 }
 370                 Pstate_num++;
 371         }
 372
 373         /* Constuct P[Min] State */
 374         if (Max_fid == 0x2A && Max_vid != 0x0) {
 375                 Pstate_fid[Pstate_num] = 0x2;
 376                 Pstate_feq[Pstate_num] =
 377                     Pstate_fid[Pstate_num] * fid_multiplier + 800;
 378                 Pstate_vid[Pstate_num] = Min_vid;
 379                 Pstate_volt[Pstate_num] = 1550 - Pstate_vid[Pstate_num] * 25;
 380                 Pstate_power[Pstate_num] =
 381                     (unsigned long long)Pstate_power[0] *
 382                     Pstate_feq[Pstate_num] * Pstate_volt[Pstate_num] *
 383                     Pstate_volt[Pstate_num] / (Pstate_feq[0] * Pstate_volt[0] *
 384                                                Pstate_volt[0]);
 385                 Pstate_num++;
 386         } else {
 387                 Pstate_fid[Pstate_num] = Start_fid;
 388                 Pstate_feq[Pstate_num] =
 389                     Pstate_fid[Pstate_num] * fid_multiplier + 800;
 390                 Pstate_vid[Pstate_num] = Min_vid;
 391                 Pstate_volt[Pstate_num] = 1550 - Pstate_vid[Pstate_num] * 25;
 392                 Pstate_power[Pstate_num] =
 393                     (unsigned long long)Pstate_power[0] *
 394                     Pstate_feq[Pstate_num] * Pstate_volt[Pstate_num] *
 395                     Pstate_volt[Pstate_num] / (Pstate_feq[0] * Pstate_volt[0] *
 396                                                Pstate_volt[0]);
 397                 Pstate_num++;
 398         }
 399
 400         /* Print Pstate freq,vid,volt,power */
 401
 402         for (index = 0; index < Pstate_num; index++) {
 403                 printk_info("Pstate_freq[%d] = %dMHz\t", index,
 404                             Pstate_feq[index]);
 405                 printk_info("Pstate_vid[%d] = %d\t", index, Pstate_vid[index]);
 406                 printk_info("Pstate_volt[%d] = %dmv\t", index,
 407                             Pstate_volt[index]);
 408                 printk_info("Pstate_power[%d] = %dmw\n", index,
 409                             Pstate_power[index]);
 410         }
 411
 412         /*
 413          * Modify the DSDT Table to put the actural _PSS package
 414          * corefeq-->Pstate_feq[index]
 415          * power-->Pstate_power[index]
 416          * transitionlatency-->0x64
 417          * busmasterlatency-->0x7,
 418          * control--> 0xE8202800| Pstate_vid[index]<<6 | Pstate_fid[index]
 419          * status --> Pstate_vid[index]<<6 | Pstate_fid[index]
 420          * Get the _PSS control method Sig.
 421          */
 422
 423         dsdt_pointer = (u8 *) dsdt;
 424         old_dsdt_length = dsdt->length;
 425         new_dsdt_length = old_dsdt_length;
 426         printk_info("DSDT reconstruction...\n");
 427         for (i = 0x20; i < new_dsdt_length; i++)
 428                 if ((*(dsdt_pointer + i) == '_')
 429                     && (*(dsdt_pointer + i + 1) == 'P')
 430                     && (*(dsdt_pointer + i + 2) == 'S')
 431                     && (*(dsdt_pointer + i + 3) == 'S')) {
 432
 433                         if ((*(dsdt_pointer + i + 4) !=
 434                              0x12) | (*(dsdt_pointer + i + 5) !=
 435                                       0x4B) | (*(dsdt_pointer + i + 6) !=
 436                                                0x10)) {
 437                                 printk_info
 438                                     ("Error:No _PSS package leader byte!\n");
 439                         } else {
 440                                 new_package_length =
 441                                     0x10B - Defpkglength * (Maxpstate -
 442                                                             Pstate_num);
 443                                 /* two Pstates length will larger than 63, so we need not worry about the length */
 444                                 if (new_package_length > 63) {
 445                                         *(dsdt_pointer + i + 5) =
 446                                             0x40 | (new_package_length & 0xf);
 447                                         *(dsdt_pointer + i + 6) =
 448                                             (new_package_length & 0xff0) >> 4;
 449                                 }
 450                                 *(dsdt_pointer + i + 7) = Pstate_num;
 451                         }
 452
 453                         if ((*(dsdt_pointer + i + 8) !=
 454                              0x12) | (*(dsdt_pointer + i + 9) !=
 455                                       0x20) | (*(dsdt_pointer + i + 10) != 0x6))
 456                                 printk_info
 457                                     ("Error:No package leader for the first Pstate!\n");
 458                         for (index = 0; index < Pstate_num; index++) {
 459                                 corefeq = Pstate_feq[index];
 460                                 power = Pstate_power[index];
 461                                 transitionlatency = 0x64;
 462                                 busmasterlatency = 0x7;
 463                                 control =
 464                                     (0x3 << 30) | /* IRT */
 465                                     (0x2 << 28) | /* RVO */
 466                                     (0x1 << 27) | /* ExtType */
 467                                     (0x2 << 20) | /* PLL_LOCK_TIME */
 468                                     (0x0 << 18) | /* MVS */
 469                                     (0x5 << 11) | /* VST */
 470                                     (Pstate_vid[index] << 6) |
 471                                     Pstate_fid[index];
 472                                 status =
 473                                     (Pstate_vid[index] << 6) |
 474                                     Pstate_fid[index];
 475                                 for (byte_index = 0; byte_index < 4;
 476                                      byte_index++) {
 477                                         *(dsdt_pointer + i + 0xC +
 478                                           Defpkglength * index + byte_index) =
 479                    corefeq >> (8 * byte_index);
 480                                         *(dsdt_pointer + i + 0xC +
 481                                           Defpkglength * index + 0x5 +
 482                                           byte_index) =
 483                    power >> (8 * byte_index);
 484                                         *(dsdt_pointer + i + 0xC +
 485                                           Defpkglength * index + 0x5 * 2 +
 486                                           byte_index) =
 487                    transitionlatency >> (8 * byte_index);
 488                                         *(dsdt_pointer + i + 0xC +
 489                                           Defpkglength * index + 0x5 * 3 +
 490                                           byte_index) =
 491                    busmasterlatency >> (8 * byte_index);
 492                                         *(dsdt_pointer + i + 0xC +
 493                                           Defpkglength * index + 0x5 * 4 +
 494                                           byte_index) =
 495                    control >> (8 * byte_index);
 496                                         *(dsdt_pointer + i + 0xC +
 497                                           Defpkglength * index + 0x5 * 5 +
 498                                           byte_index) =
 499                    status >> (8 * byte_index);
 500                                 }
 501                         }
 502                         pointer1 =
 503                             dsdt_pointer + i + 8 + Pstate_num * Defpkglength;
 504                         pointer2 =
 505                             dsdt_pointer + i + 8 + Maxpstate * Defpkglength;
 506                         while (pointer2 < dsdt_pointer + new_dsdt_length) {
 507                                 *pointer1 = *pointer2;
 508                                 pointer1++;
 509                                 pointer2++;
 510                         }
 511                         /* Recalcute the DSDT length */
 512                         new_dsdt_length =
 513                             new_dsdt_length - Defpkglength * (Maxpstate -
 514                                                               Pstate_num);
 515
 516                         /* Search the first processor(CPUx) item and recalculate the processor length */
 517                         for (j = 0; (dsdt_pointer + i - j) > dsdt_pointer; j++) {
 518                                 if ((*(dsdt_pointer + i - j) == 'C')
 519                                     && (*(dsdt_pointer + i - j + 1) == 'P')
 520                                     && (*(dsdt_pointer + i - j + 2) == 'U')) {
 521                                         processor_length =
 522                                             ((*(dsdt_pointer + i - j - 1) << 4)
 523                                              | (*(dsdt_pointer + i - j - 2) &
 524                                                 0xf));
 525                                         processor_length =
 526                                             processor_length -
 527                                             Defpkglength * (Maxpstate -
 528                                                             Pstate_num);
 529                                         *(dsdt_pointer + i - j - 2) =
 530                                             (processor_length & 0xf) | 0x40;
 531                                         *(dsdt_pointer + i - j - 1) =
 532                                             (processor_length & 0xff0) >> 4;
 533                                         break;
 534                                 }
 535                         }
 536
 537                         /* Search the first scope(_PR_) item and recalculate the scope length */
 538                         for (j = 0; (dsdt_pointer + i - j) > dsdt_pointer; j++) {
 539                                 if ((*(dsdt_pointer + i - j) == '_')
 540                                     && (*(dsdt_pointer + i - j + 1) == 'P')
 541                                     && (*(dsdt_pointer + i - j + 2) == 'R')
 542                                     && (*(dsdt_pointer + i - j + 3) == '_')) {
 543                                         scope_length =
 544                                             ((*(dsdt_pointer + i - j - 1) << 4)
 545                                              | (*(dsdt_pointer + i - j - 2) &
 546                                                 0xf));
 547                                         scope_length =
 548                                             scope_length -
 549                                             Defpkglength * (Maxpstate -
 550                                                             Pstate_num);
 551                                         *(dsdt_pointer + i - j - 2) =
 552                                             (scope_length & 0xf) | 0x40;
 553                                         *(dsdt_pointer + i - j - 1) =
 554                                             (scope_length & 0xff0) >> 4;
 555                                         break;
 556                                 }
 557                         }
 558
 559                 }
 560
 561         /* Recalculate the DSDT length and fill back to the table */
 562         *(dsdt_pointer + 0x4) = new_dsdt_length;
 563         *(dsdt_pointer + 0x5) = new_dsdt_length >> 8;
 564
 565         /*
 566          * Recalculate the DSDT checksum and fill back to the table
 567          * We must make sure the sum of the whole table is 0
 568          */
 569         sum = 0;
 570         for (i = 0; i < new_dsdt_length; i++)
 571                 if (i != 9)
 572                         sum = sum + *(dsdt_pointer + i);
 573         checksum = 0x100 - sum;
 574         *(dsdt_pointer + 0x9) = checksum;
 575
 576         /*Check the DSDT Table */
 577         /*
 578          * printk_info("The new DSDT table length is %x\n", new_dsdt_length);
 579          * printk_info("Details is as below:\n");
 580          * for(i=0; i< new_dsdt_length; i++){
 581          *      printk_info("%x\t",(unsigned char)*(dsdt_pointer+i));
 582          *      if( ((i+1)&0x7) == 0x0)
 583          *              printk_info("**0x%x**\n",i-7);
 584          *}
 585          */
 586
 587         return 1;
 588
 589 }
 590
 591 unsigned long acpi_fill_ssdt_generator(unsigned long current, char *oem_table_id) {
 592         k8acpi_write_vars();
 593         return (unsigned long) (acpigen_get_current());
 594 }
 595
 596 unsigned long write_acpi_tables(unsigned long start)
 597 {
 598         unsigned long current;
 599         acpi_rsdp_t *rsdp;
 600         acpi_rsdt_t *rsdt;
 601         acpi_hpet_t *hpet;
 602         acpi_madt_t *madt;
 603         acpi_fadt_t *fadt;
 604         acpi_facs_t *facs;
 605         acpi_header_t *dsdt;
 606         acpi_header_t *ssdt;
 607
 608         get_bus_conf();         /* it will get sblk, pci1234, hcdn, and sbdn */
 609
 610         /* Align ACPI tables to 16byte */
 611         start = (start + 0x0f) & -0x10;
 612         current = start;
 613
 614         printk_info("ACPI: Writing ACPI tables at %lx...\n", start);
 615
 616         /* We need at least an RSDP and an RSDT Table */
 617         rsdp = (acpi_rsdp_t *) current;
 618         current += sizeof(acpi_rsdp_t);
 619         rsdt = (acpi_rsdt_t *) current;
 620         current += sizeof(acpi_rsdt_t);
 621
 622         /* clear all table memory */
 623         memset((void *)start, 0, current - start);
 624
 625         acpi_write_rsdp(rsdp, rsdt);
 626         acpi_write_rsdt(rsdt);
 627
 628         /*
 629          * We explicitly add these tables later on:
 630          */
 631         /* If we want to use HPET Timers Linux wants an MADT */
 632         printk_debug("ACPI:    * HPET\n");
 633         hpet = (acpi_hpet_t *) current;
 634         current += sizeof(acpi_hpet_t);
 635         acpi_create_hpet(hpet);
 636         acpi_add_table(rsdt, hpet);
 637
 638         printk_debug("ACPI:    * MADT\n");
 639         madt = (acpi_madt_t *) current;
 640         acpi_create_madt(madt);
 641         current += madt->header.length;
 642         acpi_add_table(rsdt, madt);
 643
 644 #if 0
 645         /* SRAT */
 646         printk_debug("ACPI:    * SRAT\n");
 647         srat = (acpi_srat_t *) current;
 648         acpi_create_srat(srat);
 649         current += srat->header.length;
 650         acpi_add_table(rsdt, srat);
 651
 652         /* SLIT */
 653         printk_debug("ACPI:    * SLIT\n");
 654         slit = (acpi_slit_t *) current;
 655         acpi_create_slit(slit);
 656         current += slit->header.length;
 657         acpi_add_table(rsdt, slit);
 658 #endif
 659
 660         /* SSDT */
 661         printk_debug("ACPI:    * SSDT\n");
 662         ssdt = (acpi_header_t *)current;
 663
 664         acpi_create_ssdt_generator(ssdt, "DYNADATA");
 665         current += ssdt->length;
 666         acpi_add_table(rsdt, ssdt);
 667
 668 #if ACPI_SSDTX_NUM >= 1
 669
 670         /* same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table */
 671
 672         for (i = 1; i < sysconf.hc_possible_num; i++) { /* 0: is hc sblink */
 673                 if ((sysconf.pci1234[i] & 1) != 1)
 674                         continue;
 675                 uint8_t c;
 676                 if (i < 7) {
 677                         c = (uint8_t) ('4' + i - 1);
 678                 } else {
 679                         c = (uint8_t) ('A' + i - 1 - 6);
 680                 }
 681                 printk_debug("ACPI:    * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]);  /* pci0 and pci1 are in dsdt */
 682                 current = (current + 0x07) & -0x08;
 683                 ssdtx = (acpi_header_t *) current;
 684                 switch (sysconf.hcid[i]) {
 685                 case 1: /* 8132 */
 686                         p = AmlCode_ssdt2;
 687                         break;
 688                 case 2: /* 8151 */
 689                         p = AmlCode_ssdt3;
 690                         break;
 691                 case 3: /* 8131 */
 692                         p = AmlCode_ssdt4;
 693                         break;
 694                 default:
 695                         /* HTX no io apic */
 696                         p = AmlCode_ssdt5;
 697                         break;
 698                 }
 699                 current += ((acpi_header_t *) p)->length;
 700                 memcpy((void *)ssdtx, (void *)p, ((acpi_header_t *) p)->length);
 701                 update_ssdtx((void *)ssdtx, i);
 702                 ssdtx->checksum = 0;
 703                 ssdtx->checksum =
 704                     acpi_checksum((u8 *)ssdtx, ssdtx->length);
 705                 acpi_add_table(rsdt, ssdtx);
 706         }
 707 #endif
 708
 709         /* FACS */
 710         printk_debug("ACPI:    * FACS\n");
 711         facs = (acpi_facs_t *) current;
 712         current += sizeof(acpi_facs_t);
 713         acpi_create_facs(facs);
 714
 715         /* DSDT */
 716         printk_debug("ACPI:    * DSDT\n");
 717         dsdt = (acpi_header_t *) current;
 718         memcpy((void *)dsdt, (void *)AmlCode,
 719                ((acpi_header_t *) AmlCode)->length);
 720         if (!pstates_algorithm(dsdt))
 721                 printk_debug("pstates_algorithm error!\n");
 722         else
 723                 printk_debug("pstates_algorithm success.\n");
 724
 725         current += dsdt->length;
 726         printk_debug("ACPI:    * DSDT @ %08x Length %x\n", dsdt, dsdt->length);
 727         /* FADT */
 728         printk_debug("ACPI:    * FADT\n");
 729         fadt = (acpi_fadt_t *) current;
 730         current += sizeof(acpi_fadt_t);
 731
 732         acpi_create_fadt(fadt, facs, dsdt);
 733         acpi_add_table(rsdt, fadt);
 734
 735 #if DUMP_ACPI_TABLES == 1
 736         printk_debug("rsdp\n");
 737         dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
 738
 739         printk_debug("rsdt\n");
 740         dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
 741
 742         printk_debug("madt\n");
 743         dump_mem(madt, ((void *)madt) + madt->header.length);
 744
 745         printk_debug("srat\n");
 746         dump_mem(srat, ((void *)srat) + srat->header.length);
 747
 748         printk_debug("slit\n");
 749         dump_mem(slit, ((void *)slit) + slit->header.length);
 750
 751         printk_debug("ssdt\n");
 752         dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
 753
 754         printk_debug("fadt\n");
 755         dump_mem(fadt, ((void *)fadt) + fadt->header.length);
 756 #endif
 757
 758         printk_info("ACPI: done.\n");
 759         return current;
 760 }