2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2008 Advanced Micro Devices, Inc.
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; version 2 of the License.
10 ## This program is distributed in the hope that it will be useful,
11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ## GNU General Public License for more details.
15 ## You should have received a copy of the GNU General Public License
16 ## along with this program; if not, write to the Free Software
17 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 uses CONFIG_HAVE_MP_TABLE
24 uses CONFIG_HAVE_PIRQ_TABLE
25 uses CONFIG_HAVE_ACPI_TABLES
26 uses CONFIG_HAVE_ACPI_RESUME
27 uses CONFIG_USE_FALLBACK_IMAGE
28 uses CONFIG_HAVE_FALLBACK_BOOT
29 uses CONFIG_HAVE_HARD_RESET
30 uses CONFIG_IRQ_SLOT_COUNT
31 uses CONFIG_HAVE_OPTION_TABLE
33 uses CONFIG_MAX_PHYSICAL_CPUS
34 uses CONFIG_LOGICAL_CPUS
37 uses CONFIG_FALLBACK_SIZE
39 uses CONFIG_ROM_SECTION_SIZE
40 uses CONFIG_ROM_IMAGE_SIZE
41 uses CONFIG_ROM_SECTION_SIZE
42 uses CONFIG_ROM_SECTION_OFFSET
43 uses CONFIG_ROM_PAYLOAD
44 uses CONFIG_ROM_PAYLOAD_START
45 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
46 uses CONFIG_PAYLOAD_SIZE
48 uses CONFIG_XIP_ROM_SIZE
49 uses CONFIG_XIP_ROM_BASE
50 uses CONFIG_STACK_SIZE
52 uses CONFIG_USE_OPTION_TABLE
53 uses CONFIG_LB_CKS_RANGE_START
54 uses CONFIG_LB_CKS_RANGE_END
55 uses CONFIG_LB_CKS_LOC
56 uses CONFIG_MAINBOARD_PART_NUMBER
57 uses CONFIG_MAINBOARD_VENDOR
59 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
60 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
61 uses COREBOOT_EXTRA_VERSION
63 uses CONFIG_TTYS0_BAUD
64 uses CONFIG_TTYS0_BASE
66 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
67 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
68 uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
69 uses CONFIG_CONSOLE_SERIAL8250
70 uses CONFIG_HAVE_INIT_TIMER
73 uses CONFIG_CROSS_COMPILE
77 uses CONFIG_CONSOLE_VGA
78 uses CONFIG_PCI_ROM_RUN
79 uses CONFIG_HW_MEM_HOLE_SIZEK
80 uses CONFIG_HT_CHAIN_UNITID_BASE
81 uses CONFIG_HT_CHAIN_END_UNITID_BASE
82 uses CONFIG_SB_HT_CHAIN_ON_BUS0
84 uses CONFIG_USE_DCACHE_RAM
85 uses CONFIG_DCACHE_RAM_BASE
86 uses CONFIG_DCACHE_RAM_SIZE
87 uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
90 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
91 uses CONFIG_USE_PRINTK_IN_CAR
95 uses CONFIG_HAVE_MAINBOARD_RESOURCES
102 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
104 default CONFIG_ROM_SIZE=524288
107 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
109 #default CONFIG_FALLBACK_SIZE=131072
111 default CONFIG_FALLBACK_SIZE=0x40000
114 ## Build code for the fallback boot
116 default CONFIG_HAVE_FALLBACK_BOOT=1
119 ## Build code to reset the motherboard from coreboot
121 default CONFIG_HAVE_HARD_RESET=1
124 ## Build code to export a programmable irq routing table
126 default CONFIG_HAVE_PIRQ_TABLE=1
127 default CONFIG_IRQ_SLOT_COUNT=11
130 ## Build code to export an x86 MP table
131 ## Useful for specifying IRQ routing values
133 default CONFIG_HAVE_MP_TABLE=1
135 ## ACPI tables will be included
136 default CONFIG_HAVE_ACPI_TABLES=1
139 ## Build code to export a CMOS option table
141 default CONFIG_HAVE_OPTION_TABLE=0
144 ## Move the default coreboot cmos range off of AMD RTC registers
146 default CONFIG_LB_CKS_RANGE_START=49
147 default CONFIG_LB_CKS_RANGE_END=122
148 default CONFIG_LB_CKS_LOC=123
151 ## Build code for SMP support
152 ## Only worry about 2 micro processors
155 default CONFIG_MAX_CPUS=2
157 default CONFIG_MAX_PHYSICAL_CPUS=1
158 default CONFIG_LOGICAL_CPUS=1
161 default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
164 default CONFIG_CONSOLE_VGA=1
165 default CONFIG_PCI_ROM_RUN=1
167 # BTDC: Only one HT device on Herring.
169 #default CONFIG_HT_CHAIN_UNITID_BASE=0x6
170 default CONFIG_HT_CHAIN_UNITID_BASE=0x0
174 default CONFIG_HT_CHAIN_END_UNITID_BASE=0x1
176 #make the SB HT chain on bus 0
177 default CONFIG_SB_HT_CHAIN_ON_BUS0=1
180 ## enable CACHE_AS_RAM specifics
182 default CONFIG_USE_DCACHE_RAM=1
183 default CONFIG_DCACHE_RAM_BASE=0xc8000
184 default CONFIG_DCACHE_RAM_SIZE=0x8000
185 default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
186 default CONFIG_USE_INIT=0
189 ## Build code to setup a generic IOAPIC
191 default CONFIG_IOAPIC=1
194 ## Clean up the motherboard id strings
196 default CONFIG_MAINBOARD_PART_NUMBER="pistachio"
197 default CONFIG_MAINBOARD_VENDOR="amd"
198 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
199 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050
203 ### coreboot layout values
206 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
207 default CONFIG_ROM_IMAGE_SIZE = 65536
210 ## Use a small 8K stack
212 default CONFIG_STACK_SIZE=0x2000
215 ## Use a small 16K heap
217 default CONFIG_HEAP_SIZE=0x4000
220 ## Only use the option table in a normal image
222 #default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
223 default CONFIG_USE_OPTION_TABLE = 0
226 ## coreboot C code runs at this location in RAM
228 default CONFIG_RAMBASE=0x00004000
231 ## Load the payload from the ROM
233 default CONFIG_ROM_PAYLOAD = 1
236 ### Defaults of options that you may want to override in the target config file
240 ## The default compiler
242 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
246 ## Disable the gdb stub by default
248 default CONFIG_GDB_STUB=0
251 default CONFIG_USE_PRINTK_IN_CAR=1
254 ## The Serial Console
257 # To Enable the Serial Console
258 default CONFIG_CONSOLE_SERIAL8250=1
260 ## Select the serial console baud rate
261 default CONFIG_TTYS0_BAUD=115200
262 #default CONFIG_TTYS0_BAUD=57600
263 #default CONFIG_TTYS0_BAUD=38400
264 #default CONFIG_TTYS0_BAUD=19200
265 #default CONFIG_TTYS0_BAUD=9600
266 #default CONFIG_TTYS0_BAUD=4800
267 #default CONFIG_TTYS0_BAUD=2400
268 #default CONFIG_TTYS0_BAUD=1200
270 # Select the serial console base port
271 default CONFIG_TTYS0_BASE=0x3f8
273 # Select the serial protocol
274 # This defaults to 8 data bits, 1 stop bit, and no parity
275 default CONFIG_TTYS0_LCS=0x3
278 ### Select the coreboot loglevel
280 ## EMERG 1 system is unusable
281 ## ALERT 2 action must be taken immediately
282 ## CRIT 3 critical conditions
283 ## ERR 4 error conditions
284 ## WARNING 5 warning conditions
285 ## NOTICE 6 normal but significant condition
286 ## INFO 7 informational
287 ## CONFIG_DEBUG 8 debug-level messages
288 ## SPEW 9 Way too many details
290 ## Request this level of debugging output
291 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
292 ## At a maximum only compile in this level of debugging
293 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
296 ## Select power on after power fail setting
297 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
299 default CONFIG_VIDEO_MB=1
300 default CONFIG_GFXUMA=1
301 default CONFIG_HAVE_MAINBOARD_RESOURCES=1
308 default CONFIG_CBFS=0