2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2008 Advanced Micro Devices, Inc.
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; version 2 of the License.
10 ## This program is distributed in the hope that it will be useful,
11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ## GNU General Public License for more details.
15 ## You should have received a copy of the GNU General Public License
16 ## along with this program; if not, write to the Free Software
17 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 uses CONFIG_GENERATE_MP_TABLE
23 uses CONFIG_GENERATE_PIRQ_TABLE
24 uses CONFIG_GENERATE_ACPI_TABLES
25 uses CONFIG_HAVE_ACPI_RESUME
26 uses CONFIG_USE_FALLBACK_IMAGE
27 uses CONFIG_HAVE_FALLBACK_BOOT
28 uses CONFIG_HAVE_HARD_RESET
29 uses CONFIG_IRQ_SLOT_COUNT
30 uses CONFIG_HAVE_OPTION_TABLE
32 uses CONFIG_MAX_PHYSICAL_CPUS
33 uses CONFIG_LOGICAL_CPUS
36 uses CONFIG_FALLBACK_SIZE
38 uses CONFIG_ROM_SECTION_SIZE
39 uses CONFIG_ROM_IMAGE_SIZE
40 uses CONFIG_ROM_SECTION_SIZE
41 uses CONFIG_ROM_SECTION_OFFSET
42 uses CONFIG_ROM_PAYLOAD
43 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
45 uses CONFIG_XIP_ROM_SIZE
46 uses CONFIG_XIP_ROM_BASE
47 uses CONFIG_STACK_SIZE
49 uses CONFIG_USE_OPTION_TABLE
50 uses CONFIG_LB_CKS_RANGE_START
51 uses CONFIG_LB_CKS_RANGE_END
52 uses CONFIG_LB_CKS_LOC
53 uses CONFIG_MAINBOARD_PART_NUMBER
54 uses CONFIG_MAINBOARD_VENDOR
56 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
57 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
58 uses COREBOOT_EXTRA_VERSION
60 uses CONFIG_TTYS0_BAUD
61 uses CONFIG_TTYS0_BASE
63 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
64 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
65 uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
66 uses CONFIG_CONSOLE_SERIAL8250
67 uses CONFIG_HAVE_INIT_TIMER
70 uses CONFIG_CROSS_COMPILE
74 uses CONFIG_CONSOLE_VGA
75 uses CONFIG_PCI_ROM_RUN
76 uses CONFIG_HW_MEM_HOLE_SIZEK
77 uses CONFIG_HT_CHAIN_UNITID_BASE
78 uses CONFIG_HT_CHAIN_END_UNITID_BASE
79 uses CONFIG_SB_HT_CHAIN_ON_BUS0
81 uses CONFIG_USE_DCACHE_RAM
82 uses CONFIG_DCACHE_RAM_BASE
83 uses CONFIG_DCACHE_RAM_SIZE
84 uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
87 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
88 uses CONFIG_USE_PRINTK_IN_CAR
92 uses CONFIG_HAVE_MAINBOARD_RESOURCES
99 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
101 default CONFIG_ROM_SIZE=524288
104 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
106 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
109 ## Build code for the fallback boot
111 default CONFIG_HAVE_FALLBACK_BOOT=1
114 ## Build code to reset the motherboard from coreboot
116 default CONFIG_HAVE_HARD_RESET=1
119 ## Build code to export a programmable irq routing table
121 default CONFIG_GENERATE_PIRQ_TABLE=1
122 default CONFIG_IRQ_SLOT_COUNT=11
125 ## Build code to export an x86 MP table
126 ## Useful for specifying IRQ routing values
128 default CONFIG_GENERATE_MP_TABLE=1
130 ## ACPI tables will be included
131 default CONFIG_GENERATE_ACPI_TABLES=1
134 ## Build code to export a CMOS option table
136 default CONFIG_HAVE_OPTION_TABLE=0
139 ## Move the default coreboot cmos range off of AMD RTC registers
141 default CONFIG_LB_CKS_RANGE_START=49
142 default CONFIG_LB_CKS_RANGE_END=122
143 default CONFIG_LB_CKS_LOC=123
146 ## Build code for SMP support
147 ## Only worry about 2 micro processors
150 default CONFIG_MAX_CPUS=2
152 default CONFIG_MAX_PHYSICAL_CPUS=1
153 default CONFIG_LOGICAL_CPUS=1
156 default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
159 default CONFIG_CONSOLE_VGA=1
160 default CONFIG_PCI_ROM_RUN=1
162 # BTDC: Only one HT device on Herring.
164 #default CONFIG_HT_CHAIN_UNITID_BASE=0x6
165 default CONFIG_HT_CHAIN_UNITID_BASE=0x0
169 default CONFIG_HT_CHAIN_END_UNITID_BASE=0x1
171 #make the SB HT chain on bus 0
172 default CONFIG_SB_HT_CHAIN_ON_BUS0=1
175 ## enable CACHE_AS_RAM specifics
177 default CONFIG_USE_DCACHE_RAM=1
178 default CONFIG_DCACHE_RAM_BASE=0xc8000
179 default CONFIG_DCACHE_RAM_SIZE=0x8000
180 default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
181 default CONFIG_USE_INIT=0
184 ## Build code to setup a generic IOAPIC
186 default CONFIG_IOAPIC=1
189 ## Clean up the motherboard id strings
191 default CONFIG_MAINBOARD_PART_NUMBER="pistachio"
192 default CONFIG_MAINBOARD_VENDOR="amd"
193 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
194 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050
198 ### coreboot layout values
201 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
202 default CONFIG_ROM_IMAGE_SIZE = 65536
205 ## Use a small 8K stack
207 default CONFIG_STACK_SIZE=0x2000
210 ## Use a small 16K heap
212 default CONFIG_HEAP_SIZE=0x4000
215 ## Only use the option table in a normal image
217 #default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
218 default CONFIG_USE_OPTION_TABLE = 0
221 ## coreboot C code runs at this location in RAM
223 default CONFIG_RAMBASE=0x00004000
226 ## Load the payload from the ROM
228 default CONFIG_ROM_PAYLOAD = 1
231 ### Defaults of options that you may want to override in the target config file
235 ## The default compiler
237 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
241 ## Disable the gdb stub by default
243 default CONFIG_GDB_STUB=0
246 default CONFIG_USE_PRINTK_IN_CAR=1
249 ## The Serial Console
252 # To Enable the Serial Console
253 default CONFIG_CONSOLE_SERIAL8250=1
255 ## Select the serial console baud rate
256 default CONFIG_TTYS0_BAUD=115200
257 #default CONFIG_TTYS0_BAUD=57600
258 #default CONFIG_TTYS0_BAUD=38400
259 #default CONFIG_TTYS0_BAUD=19200
260 #default CONFIG_TTYS0_BAUD=9600
261 #default CONFIG_TTYS0_BAUD=4800
262 #default CONFIG_TTYS0_BAUD=2400
263 #default CONFIG_TTYS0_BAUD=1200
265 # Select the serial console base port
266 default CONFIG_TTYS0_BASE=0x3f8
268 # Select the serial protocol
269 # This defaults to 8 data bits, 1 stop bit, and no parity
270 default CONFIG_TTYS0_LCS=0x3
273 ### Select the coreboot loglevel
275 ## EMERG 1 system is unusable
276 ## ALERT 2 action must be taken immediately
277 ## CRIT 3 critical conditions
278 ## ERR 4 error conditions
279 ## WARNING 5 warning conditions
280 ## NOTICE 6 normal but significant condition
281 ## INFO 7 informational
282 ## CONFIG_DEBUG 8 debug-level messages
283 ## SPEW 9 Way too many details
285 ## Request this level of debugging output
286 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
287 ## At a maximum only compile in this level of debugging
288 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
291 ## Select power on after power fail setting
292 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
294 default CONFIG_VIDEO_MB=1
295 default CONFIG_GFXUMA=1
296 default CONFIG_HAVE_MAINBOARD_RESOURCES=1