2 * This file is part of the coreboot project.
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #ifndef _PERSIMMON_CFG_H_
22 #define _PERSIMMON_CFG_H_
30 #define BIOS_SIZE_1M 0
31 #define BIOS_SIZE_2M 1
32 #define BIOS_SIZE_4M 3
33 #define BIOS_SIZE_8M 7
35 /* In SB800, default ROM size is 1M Bytes, if your platform ROM
36 * bigger than 1M you have to set the ROM size outside CIMx module and
37 * before AGESA module get call.
40 #if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
41 #define BIOS_SIZE BIOS_SIZE_1M
42 #elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
43 #define BIOS_SIZE BIOS_SIZE_2M
44 #elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1
45 #define BIOS_SIZE BIOS_SIZE_4M
46 #elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1
47 #define BIOS_SIZE BIOS_SIZE_8M
52 * @def SPREAD_SPECTRUM
54 * 0 - Disable Spread Spectrum function
55 * 1 - Enable Spread Spectrum function
57 #define SPREAD_SPECTRUM 0
69 * @brief bit[0-6] used to control USB
72 * Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0
73 * Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1
74 * Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2
75 * Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3
76 * Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4
77 * Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5
78 * Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6
80 #define USB_CONFIG 0x7F
84 * @breif bit[0-4] used for PCI Slots Clock Control,
87 * PCI SLOT 0 define at BIT0
88 * PCI SLOT 1 define at BIT1
89 * PCI SLOT 2 define at BIT2
90 * PCI SLOT 3 define at BIT3
91 * PCI SLOT 4 define at BIT4
93 #define PCI_CLOCK_CTRL 0x1F
96 * @def SATA_CONTROLLER
97 * @breif INCHIP Sata Controller
99 #define SATA_CONTROLLER CIMX_OPTION_ENABLED
103 * @breif INCHIP Sata Controller Mode
104 * NOTE: DO NOT ALLOW SATA & IDE use same mode
106 #define SATA_MODE CONFIG_SB800_SATA_MODE
109 * @breif INCHIP Sata IDE Controller Mode
111 #define IDE_LEGACY_MODE 0
112 #define IDE_NATIVE_MODE 1
116 * @breif INCHIP Sata IDE Controller Mode
117 * NOTE: DO NOT ALLOW SATA & IDE use same mode
119 #define SATA_IDE_MODE IDE_LEGACY_MODE
122 * @def EXTERNAL_CLOCK
123 * @brief 00/10: Reference clock from crystal oscillator via
124 * PAD_XTALI and PAD_XTALO
126 * @def INTERNAL_CLOCK
127 * @brief 01/11: Reference clock from internal clock through
128 * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
130 #define EXTERNAL_CLOCK 0x00
131 #define INTERNAL_CLOCK 0x01
133 /* NOTE: inagua have to using internal clock,
134 * otherwise can not detect sata drive
136 #define SATA_CLOCK_SOURCE INTERNAL_CLOCK
139 * @def SATA_PORT_MULT_CAP_RESERVED
142 #define SATA_PORT_MULT_CAP_RESERVED 1
147 * @brief Detect Azalia controller automatically.
149 * @def AZALIA_DISABLE
150 * @brief Disable Azalia controller.
153 * @brief Enable Azalia controller.
155 #define AZALIA_AUTO 0
156 #define AZALIA_DISABLE 1
157 #define AZALIA_ENABLE 2
160 * @breif INCHIP HDA controller
162 #define AZALIA_CONTROLLER AZALIA_AUTO
165 * @def AZALIA_PIN_CONFIG
170 #define AZALIA_PIN_CONFIG 1
173 * @def AZALIA_SDIN_PIN
175 * SDIN0 is define at BIT0 & BIT1
178 * 10 - As a Azalia SDIN pin
179 * SDIN1 is define at BIT2 & BIT3
180 * SDIN2 is define at BIT4 & BIT5
181 * SDIN3 is define at BIT6 & BIT7
183 //#define AZALIA_SDIN_PIN 0xAA
184 #define AZALIA_SDIN_PIN 0x2A
187 * @def GPP_CONTROLLER
189 #define GPP_CONTROLLER CIMX_OPTION_ENABLED
193 * @brief GPP Link Configuration
194 * four possible configuration:
200 #define GPP_CFGMODE GPP_CFGMODE_X1111
207 #define NB_SB_GEN2 TRUE
214 #define SB_GPP_GEN2 TRUE
217 * @def SB_GPP_UNHIDE_PORTS
218 * TRUE - ports visable always, even port empty
219 * FALSE - ports invisable if port empty
221 #define SB_GPP_UNHIDE_PORTS FALSE
230 const static CODECENTRY persimmon_codec_alc269[] =
244 {0xff, 0xffffffff} /* end of table */
247 const static CODECTBLLIST persimmon_codec_tablelist[] =
249 {0x010ec0269, (CODECENTRY*)&persimmon_codec_alc269[0]},
250 {0x0FFFFFFFFUL, (CODECENTRY*)0x0FFFFFFFFUL}
254 * @def AZALIA_OEM_VERB_TABLE
255 * Mainboard specific cocec verb table list
257 #define AZALIA_OEM_VERB_TABLE (&persimmon_codec_tablelist[0])