2 * This file is part of the coreboot project.
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
21 #include <device/pci.h>
22 #include <device/pci_ids.h>
26 #include <cpu/amd/amdfam14.h>
27 #include "agesawrapper.h"
28 #if CONFIG_AMD_SB_CIMX
33 /* Global variables for MB layouts and these will be shared by irqtable mptable
34 * and acpi_tables busnum is default.
41 * Here you only need to set value in pci1234 for HT-IO that could be installed or not
42 * You may need to preset pci1234 for HTIO board,
43 * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
52 static u32 get_bus_conf_done = 0;
55 void get_bus_conf(void)
63 if (get_bus_conf_done == 1)
64 return; /* do it only once */
66 get_bus_conf_done = 1;
69 * This is the call to AmdInitLate. It is really in the wrong place, conceptually,
70 * but functionally within the coreboot model, this is the best place to make the
71 * call. The logically correct place to call AmdInitLate is after PCI scan is done,
72 * after the decision about S3 resume is made, and before the system tables are
73 * written into RAM. The routine that is responsible for writing the tables is
74 * "write_tables", called near the end of "hardwaremain". There is no platform
75 * specific entry point between the S3 resume decision point and the call to
76 * "write_tables", and the next platform specific entry points are the calls to
77 * the ACPI table write functions. The first of ose would seem to be the right
78 * place, but other table write functions, e.g. the PIRQ table write function, are
79 * called before the ACPI tables are written. This routine is called at the beginning
80 * of each of the write functions called prior to the ACPI write functions, so this
81 * becomes the best place for this call.
83 status = agesawrapper_amdinitlate();
85 printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status);
90 for (i = 0; i < 3; i++) {
94 for (i = 0; i < 256; i++) {
95 bus_type[i] = 0; /* default ISA bus. */
99 bus_type[0] = 1; /* pci */
101 // bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff;
102 bus_sb800[0] = (pci1234x[0] >> 16) & 0xff;
105 dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4));
110 bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
112 bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
114 for (j = bus_sb800[1]; j < bus_isa; j++)
118 for (i = 0; i < 4; i++) {
119 dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, i));
121 bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
122 bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
126 for (j = bus_sb800[2]; j < bus_isa; j++)
130 /* I/O APICs: APIC ID Version State Address */
132 apicid_base = CONFIG_MAX_CPUS;
133 apicid_sb800 = apicid_base;
135 #if CONFIG_AMD_SB_CIMX