2 * This file is part of the LinuxBIOS project.
4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <console/console.h>
21 #include <device/device.h>
23 #include <cpu/x86/msr.h>
24 #include <cpu/amd/lxdef.h>
25 #include <device/pci_def.h>
26 #include "../../../southbridge/amd/cs5536/cs5536.h"
29 /* Print the platform configuration - do before PCI init or it will not
34 #if DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
39 int cpu_msr_defs[] = { CPU_BC_L2_CONF, CPU_IM_CONFIG, CPU_DM_CONFIG0,
40 CPU_RCONF_DEFAULT, CPU_RCONF_BYPASS, CPU_RCONF_A0_BF,
41 CPU_RCONF_C0_DF, CPU_RCONF_E0_FF, CPU_RCONF_SMM, CPU_RCONF_DMM,
42 GLCP_DELAY_CONTROLS, GL_END
45 int gliu0_msr_defs[] = { MSR_GLIU0_BASE1, MSR_GLIU0_BASE2,
46 MSR_GLIU0_BASE4, MSR_GLIU0_BASE5, MSR_GLIU0_BASE6,
47 GLIU0_P2D_BMO_0, GLIU0_P2D_BMO_1, MSR_GLIU0_SYSMEM,
48 GLIU0_P2D_RO_0, GLIU0_P2D_RO_1, GLIU0_P2D_RO_2,
49 MSR_GLIU0_SHADOW, GLIU0_IOD_BM_0, GLIU0_IOD_BM_1,
50 GLIU0_IOD_BM_2, GLIU0_IOD_SC_0, GLIU0_IOD_SC_1, GLIU0_IOD_SC_2,
51 GLIU0_IOD_SC_3, GLIU0_IOD_SC_4, GLIU0_IOD_SC_5,
52 GLIU0_GLD_MSR_COH, GL_END
55 int gliu1_msr_defs[] = { MSR_GLIU1_BASE1, MSR_GLIU1_BASE2,
56 MSR_GLIU1_BASE3, MSR_GLIU1_BASE4, MSR_GLIU1_BASE5,
57 MSR_GLIU1_BASE6, MSR_GLIU1_BASE7, MSR_GLIU1_BASE8,
58 MSR_GLIU1_BASE9, MSR_GLIU1_BASE10, GLIU1_P2D_R_0,
59 GLIU1_P2D_R_1, GLIU1_P2D_R_2, GLIU1_P2D_R_3, MSR_GLIU1_SHADOW,
60 GLIU1_IOD_BM_0, GLIU1_IOD_BM_1, GLIU1_IOD_BM_2, GLIU1_IOD_SC_0,
61 GLIU1_IOD_SC_1, GLIU1_IOD_SC_2, GLIU1_IOD_SC_3,
62 GLIU1_GLD_MSR_COH, GL_END
65 int rconf_msr[] = { CPU_RCONF0, CPU_RCONF1, CPU_RCONF2, CPU_RCONF3,
66 CPU_RCONF4, CPU_RCONF5, CPU_RCONF6, CPU_RCONF7, GL_END
69 int cs5536_msr[] = { MDD_LBAR_GPIO, MDD_LBAR_FLSH0, MDD_LBAR_FLSH1,
70 MDD_LEG_IO, MDD_PIN_OPT, MDD_IRQM_ZLOW, MDD_IRQM_ZHIGH,
74 int pci_msr[] = { GLPCI_CTRL, GLPCI_ARB, GLPCI_REN, GLPCI_A0_BF,
75 GLPCI_C0_DF, GLPCI_E0_FF, GLPCI_RC0, GLPCI_RC1, GLPCI_RC2,
76 GLPCI_RC3, GLPCI_ExtMSR, GLPCI_SPARE, GL_END
79 int dma_msr[] = { MDD_DMA_MAP, MDD_DMA_SHAD1, MDD_DMA_SHAD2,
80 MDD_DMA_SHAD3, MDD_DMA_SHAD4, MDD_DMA_SHAD5, MDD_DMA_SHAD6,
81 MDD_DMA_SHAD7, MDD_DMA_SHAD8, MDD_DMA_SHAD9, GL_END
84 printk_debug("---------- CPU ------------\n");
86 for (i = 0; cpu_msr_defs[i] != GL_END; i++) {
87 msr = rdmsr(cpu_msr_defs[i]);
88 printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n",
89 cpu_msr_defs[i], msr.hi, msr.lo);
92 printk_debug("---------- GLIU 0 ------------\n");
94 for (i = 0; gliu0_msr_defs[i] != GL_END; i++) {
95 msr = rdmsr(gliu0_msr_defs[i]);
96 printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n",
97 gliu0_msr_defs[i], msr.hi, msr.lo);
100 printk_debug("---------- GLIU 1 ------------\n");
102 for (i = 0; gliu1_msr_defs[i] != GL_END; i++) {
103 msr = rdmsr(gliu1_msr_defs[i]);
104 printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n",
105 gliu1_msr_defs[i], msr.hi, msr.lo);
108 printk_debug("---------- RCONF ------------\n");
110 for (i = 0; rconf_msr[i] != GL_END; i++) {
111 msr = rdmsr(rconf_msr[i]);
112 printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", rconf_msr[i],
116 printk_debug("---------- VARIA ------------\n");
117 msr = rdmsr(0x51300010);
118 printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51300010, msr.hi,
121 msr = rdmsr(0x51400015);
122 printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51400015, msr.hi,
125 printk_debug("---------- DIVIL IRQ ------------\n");
126 msr = rdmsr(MDD_IRQM_YLOW);
127 printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YLOW, msr.hi,
129 msr = rdmsr(MDD_IRQM_YHIGH);
130 printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YHIGH,
132 msr = rdmsr(MDD_IRQM_ZLOW);
133 printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZLOW, msr.hi,
135 msr = rdmsr(MDD_IRQM_ZHIGH);
136 printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZHIGH,
139 printk_debug("---------- PCI ------------\n");
141 for (i = 0; pci_msr[i] != GL_END; i++) {
142 msr = rdmsr(pci_msr[i]);
143 printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", pci_msr[i],
147 printk_debug("---------- LPC/UART DMA ------------\n");
149 for (i = 0; dma_msr[i] != GL_END; i++) {
150 msr = rdmsr(dma_msr[i]);
151 printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", dma_msr[i],
155 printk_debug("---------- CS5536 ------------\n");
157 for (i = 0; cs5536_msr[i] != GL_END; i++) {
158 msr = rdmsr(cs5536_msr[i]);
159 printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", cs5536_msr[i],
163 iol = inl(GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
164 printk_debug("IOR 0x%08X is now 0x%08X\n",
165 GPIO_IO_BASE + GPIOL_INPUT_ENABLE, iol);
166 iol = inl(GPIOL_EVENTS_ENABLE);
167 printk_debug("IOR 0x%08X is now 0x%08X\n",
168 GPIO_IO_BASE + GPIOL_EVENTS_ENABLE, iol);
169 iol = inl(GPIOL_INPUT_INVERT_ENABLE);
170 printk_debug("IOR 0x%08X is now 0x%08X\n",
171 GPIO_IO_BASE + GPIOL_INPUT_INVERT_ENABLE, iol);
172 iol = inl(GPIO_MAPPER_X);
173 printk_debug("IOR 0x%08X is now 0x%08X\n", GPIO_IO_BASE + GPIO_MAPPER_X,
175 #endif //DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
178 static void init(struct device *dev)
180 printk_debug("Norwich ENTER %s\n", __FUNCTION__);
181 printk_debug("Norwich EXIT %s\n", __FUNCTION__);
184 static void enable_dev(struct device *dev)
186 dev->ops->init = init;
189 struct chip_operations mainboard_amd_norwich_ops = {
190 CHIP_NAME("AMD Norwich Mainboard")
191 .enable_dev = enable_dev,