src/mainboard/amd/mahogany/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2010 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 #define RC0 (6<<8)
  21 #define RC1 (7<<8)
  22
  23 #define SMBUS_HUB 0x71
  24
  25 #include <stdint.h>
  26 #include <string.h>
  27 #include <device/pci_def.h>
  28 #include <arch/io.h>
  29 #include <device/pnp_def.h>
  30 #include <arch/romcc_io.h>
  31 #include <cpu/x86/lapic.h>
  32 #include <pc80/mc146818rtc.h>
  33 #include <console/console.h>
  34 #include <spd.h>
  35
  36 #include <cpu/amd/model_fxx_rev.h>
  37 #include "northbridge/amd/amdk8/raminit.h"
  38 #include "cpu/amd/model_fxx/apic_timer.c"
  39 #include "lib/delay.c"
  40
  41 #include "cpu/x86/lapic/boot_cpu.c"
  42 #include "northbridge/amd/amdk8/reset_test.c"
  43 #include "superio/ite/it8718f/it8718f_early_serial.c"
  44 #include <usbdebug.h>
  45
  46 #include "cpu/x86/mtrr/earlymtrr.c"
  47 #include "cpu/x86/bist.h"
  48
  49 #include "northbridge/amd/amdk8/setup_resource_map.c"
  50
  51 #include "southbridge/amd/rs780/rs780_early_setup.c"
  52 #include "southbridge/amd/sb700/sb700_early_setup.c"
  53 #include "northbridge/amd/amdk8/debug.c" /* After sb700_early_setup.c! */
  54
  55 /* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
  56 static void memreset(int controllers, const struct mem_controller *ctrl)
  57 {
  58 }
  59
  60 /* called in raminit_f.c */
  61 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  62 {
  63 }
  64
  65 /*called in raminit_f.c */
  66 static inline int spd_read_byte(u32 device, u32 address)
  67 {
  68         return smbus_read_byte(device, address);
  69 }
  70
  71 #include "northbridge/amd/amdk8/amdk8.h"
  72 #include "northbridge/amd/amdk8/incoherent_ht.c"
  73 #include "northbridge/amd/amdk8/raminit_f.c"
  74 #include "northbridge/amd/amdk8/coherent_ht.c"
  75 #include "lib/generic_sdram.c"
  76 #include "resourcemap.c"
  77
  78 #include "cpu/amd/dualcore/dualcore.c"
  79
  80
  81 #include "cpu/amd/car/post_cache_as_ram.c"
  82
  83 #include "cpu/amd/model_fxx/init_cpus.c"
  84
  85 #include "cpu/amd/model_fxx/fidvid.c"
  86
  87 #include "northbridge/amd/amdk8/early_ht.c"
  88
  89 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  90 {
  91         static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
  92         int needs_reset = 0;
  93         u32 bsp_apicid = 0;
  94         msr_t msr;
  95         struct cpuid_result cpuid1;
  96         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
  97
  98         if (!cpu_init_detectedx && boot_cpu()) {
  99                 /* Nothing special needs to be done to find bus 0 */
 100                 /* Allow the HT devices to be found */
 101                 enumerate_ht_chain();
 102
 103                 /* sb700_lpc_port80(); */
 104                 sb700_pci_port80();
 105         }
 106
 107         if (bist == 0) {
 108                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 109         }
 110
 111         enable_rs780_dev8();
 112         sb700_lpc_init();
 113
 114         it8718f_enable_serial(0, CONFIG_TTYS0_BASE);
 115         uart_init();
 116
 117 #if CONFIG_USBDEBUG
 118         sb700_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
 119         early_usbdebug_init();
 120 #endif
 121
 122         console_init();
 123
 124         /* Halt if there was a built in self test failure */
 125         report_bist_failure(bist);
 126         printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid);
 127
 128         setup_mahogany_resource_map();
 129
 130         setup_coherent_ht_domain();
 131
 132 #if CONFIG_LOGICAL_CPUS==1
 133         /* It is said that we should start core1 after all core0 launched */
 134         wait_all_core0_started();
 135         start_other_cores();
 136 #endif
 137         wait_all_aps_started(bsp_apicid);
 138
 139         ht_setup_chains_x(sysinfo);
 140
 141         /* run _early_setup before soft-reset. */
 142         rs780_early_setup();
 143         sb700_early_setup();
 144
 145         /* Check to see if processor is capable of changing FIDVID  */
 146         /* otherwise it will throw a GP# when reading FIDVID_STATUS */
 147         cpuid1 = cpuid(0x80000007);
 148         if( (cpuid1.edx & 0x6) == 0x6 ) {
 149
 150                 /* Read FIDVID_STATUS */
 151                 msr=rdmsr(0xc0010042);
 152                 printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 153
 154                 enable_fid_change();
 155                 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 156                 init_fidvid_bsp(bsp_apicid);
 157
 158                 /* show final fid and vid */
 159                 msr=rdmsr(0xc0010042);
 160                 printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 161
 162         } else {
 163                 printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
 164         }
 165
 166         needs_reset = optimize_link_coherent_ht();
 167         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 168         rs780_htinit();
 169         printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
 170
 171         if (needs_reset) {
 172                 print_info("ht reset -\n");
 173                 soft_reset();
 174         }
 175
 176         allow_all_aps_stop(bsp_apicid);
 177
 178         /* It's the time to set ctrl now; */
 179         printk(BIOS_DEBUG, "sysinfo->nodes: %2x  sysinfo->ctrl: %p  spd_addr: %p\n",
 180                      sysinfo->nodes, sysinfo->ctrl, spd_addr);
 181         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 182         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 183
 184         rs780_before_pci_init();
 185         sb700_before_pci_init();
 186
 187         post_cache_as_ram();
 188 }
 189