src/mainboard/amd/mahogany/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2010 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 #define RC0 (6<<8)
  21 #define RC1 (7<<8)
  22
  23 #define SMBUS_HUB 0x71
  24
  25 #include <stdint.h>
  26 #include <string.h>
  27 #include <device/pci_def.h>
  28 #include <arch/io.h>
  29 #include <device/pnp_def.h>
  30 #include <arch/romcc_io.h>
  31 #include <cpu/x86/lapic.h>
  32 #include <pc80/mc146818rtc.h>
  33 #include <console/console.h>
  34 #include <spd.h>
  35 #include <cpu/amd/model_fxx_rev.h>
  36 #include "northbridge/amd/amdk8/raminit.h"
  37 #include "cpu/amd/model_fxx/apic_timer.c"
  38 #include "lib/delay.c"
  39 #include "cpu/x86/lapic/boot_cpu.c"
  40 #include "northbridge/amd/amdk8/reset_test.c"
  41 #include "superio/ite/it8718f/early_serial.c"
  42 #include "cpu/x86/mtrr/earlymtrr.c"
  43 #include "cpu/x86/bist.h"
  44 #include "northbridge/amd/amdk8/setup_resource_map.c"
  45 #include "southbridge/amd/rs780/early_setup.c"
  46 #include "southbridge/amd/sb700/sb700.h"
  47 #include "southbridge/amd/sb700/smbus.h"
  48 #include "northbridge/amd/amdk8/debug.c" /* After sb700/early_setup.c! */
  49
  50 static void memreset(int controllers, const struct mem_controller *ctrl) { }
  51 static void activate_spd_rom(const struct mem_controller *ctrl) { }
  52
  53 static inline int spd_read_byte(u32 device, u32 address)
  54 {
  55         return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
  56 }
  57
  58 #include "northbridge/amd/amdk8/amdk8.h"
  59 #include "northbridge/amd/amdk8/incoherent_ht.c"
  60 #include "northbridge/amd/amdk8/raminit_f.c"
  61 #include "northbridge/amd/amdk8/coherent_ht.c"
  62 #include "lib/generic_sdram.c"
  63 #include "resourcemap.c"
  64 #include "cpu/amd/dualcore/dualcore.c"
  65 #include "cpu/amd/car/post_cache_as_ram.c"
  66 #include "cpu/amd/model_fxx/init_cpus.c"
  67 #include "cpu/amd/model_fxx/fidvid.c"
  68 #include "northbridge/amd/amdk8/early_ht.c"
  69
  70 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  71 {
  72         static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
  73         int needs_reset = 0;
  74         u32 bsp_apicid = 0;
  75         msr_t msr;
  76         struct cpuid_result cpuid1;
  77         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
  78
  79         if (!cpu_init_detectedx && boot_cpu()) {
  80                 /* Nothing special needs to be done to find bus 0 */
  81                 /* Allow the HT devices to be found */
  82                 enumerate_ht_chain();
  83                 /* sb7xx_51xx_lpc_port80(); */
  84                 sb7xx_51xx_pci_port80();
  85         }
  86
  87         if (bist == 0)
  88                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
  89
  90         enable_rs780_dev8();
  91         sb7xx_51xx_lpc_init();
  92
  93         it8718f_enable_serial(0, CONFIG_TTYS0_BASE);
  94
  95         console_init();
  96
  97         /* Halt if there was a built in self test failure */
  98         report_bist_failure(bist);
  99         printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid);
 100
 101         setup_mahogany_resource_map();
 102
 103         setup_coherent_ht_domain();
 104
 105 #if CONFIG_LOGICAL_CPUS==1
 106         /* It is said that we should start core1 after all core0 launched */
 107         wait_all_core0_started();
 108         start_other_cores();
 109 #endif
 110         wait_all_aps_started(bsp_apicid);
 111
 112         ht_setup_chains_x(sysinfo);
 113
 114         /* run _early_setup before soft-reset. */
 115         rs780_early_setup();
 116         sb7xx_51xx_early_setup();
 117
 118         /* Check to see if processor is capable of changing FIDVID  */
 119         /* otherwise it will throw a GP# when reading FIDVID_STATUS */
 120         cpuid1 = cpuid(0x80000007);
 121         if ((cpuid1.edx & 0x6) == 0x6) {
 122                 /* Read FIDVID_STATUS */
 123                 msr=rdmsr(0xc0010042);
 124                 printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 125
 126                 enable_fid_change();
 127                 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 128                 init_fidvid_bsp(bsp_apicid);
 129
 130                 /* show final fid and vid */
 131                 msr=rdmsr(0xc0010042);
 132                 printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 133         } else {
 134                 printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
 135         }
 136
 137         needs_reset = optimize_link_coherent_ht();
 138         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 139         rs780_htinit();
 140         printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
 141
 142         if (needs_reset) {
 143                 print_info("ht reset -\n");
 144                 soft_reset();
 145         }
 146
 147         allow_all_aps_stop(bsp_apicid);
 148
 149         /* It's the time to set ctrl now; */
 150         printk(BIOS_DEBUG, "sysinfo->nodes: %2x  sysinfo->ctrl: %p  spd_addr: %p\n",
 151                      sysinfo->nodes, sysinfo->ctrl, spd_addr);
 152         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 153         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 154
 155         rs780_before_pci_init();
 156         sb7xx_51xx_before_pci_init();
 157
 158         post_cache_as_ram();
 159 }