2 * This file is part of the coreboot project.
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <console/console.h>
22 #include <arch/smp/mpspec.h>
23 #include <device/pci.h>
28 #include <cpu/x86/lapic.h>
29 #include <SBPLATFORM.h>
31 #define IO_APIC_ID CONFIG_MAX_PHYSICAL_CPUS + 1
32 extern u8 bus_sb800[2];
35 extern u32 bus_type[256];
36 extern u32 sbdn_sb800;
40 0x0B,0x0A,0x0B,0x05,0x1F,0x1F,0x1F,0x1F,0x50,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
41 0x1F,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
42 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
43 0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
44 0x0A,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
48 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
49 0x1F,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
50 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
51 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
52 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
56 static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length)
58 mc->mpc_length += length;
59 mc->mpc_entry_count++;
61 static void my_smp_write_bus(struct mp_config_table *mc,
62 unsigned char id, const char *bustype)
64 struct mpc_config_bus *mpc;
65 mpc = smp_next_mpc_entry(mc);
66 memset(mpc, '\0', sizeof(*mpc));
67 mpc->mpc_type = MP_BUS;
69 memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
70 smp_add_mpc_entry(mc, sizeof(*mpc));
72 static void *smp_write_config_table(void *v)
74 struct mp_config_table *mc;
77 unsigned apic_version;
78 unsigned cpu_features;
79 unsigned cpu_feature_flags;
80 struct cpuid_result result;
81 unsigned long cpu_flag;
83 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
85 mptable_init(mc, LAPIC_ADDR);
86 memcpy(mc->mpc_oem, "AMD ", 8);
88 /*Inagua used dure core cpu with one die */
89 boot_apic_id = lapicid();
90 apic_version = lapic_read(LAPIC_LVR) & 0xff;
92 cpu_features = result.eax;
93 cpu_feature_flags = result.edx;
94 cpu_flag = MPC_CPU_ENABLED | MPC_CPU_BOOTPROCESSOR;
95 smp_write_processor(mc,
97 cpu_flag, cpu_features, cpu_feature_flags
100 cpu_flag = MPC_CPU_ENABLED;
101 smp_write_processor(mc,
103 cpu_flag, cpu_features, cpu_feature_flags
108 //mptable_write_buses(mc, NULL, &bus_isa);
109 my_smp_write_bus(mc, 0, "PCI ");
110 my_smp_write_bus(mc, 1, "PCI ");
112 my_smp_write_bus(mc, bus_isa, "ISA ");
114 /* I/O APICs: APIC ID Version State Address */
120 ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
122 /* Set IO APIC ID onto IO_APIC_ID */
123 write32 (dword, 0x00);
124 write32 (dword + 0x10, IO_APIC_ID << 24);
125 apicid_sb800 = IO_APIC_ID;
126 smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
128 /* PIC IRQ routine */
129 for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
131 outb(picr_data[byte], 0xC01);
134 /* APIC IRQ routine */
135 for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
136 outb(byte | 0x80, 0xC00);
137 outb(intr_data[byte], 0xC01);
140 /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
141 #define IO_LOCAL_INT(type, intr, apicid, pin) \
142 smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
144 //mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
145 /*I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */
146 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_sb800, 0x0);
147 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_sb800, 0x1);
148 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x2, apicid_sb800, 0x2);
149 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, apicid_sb800, 0x3);
150 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, apicid_sb800, 0x4);
151 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, 0x49, apicid_sb800, 0x11);
152 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x6, apicid_sb800, 0x6);
153 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x7, apicid_sb800, 0x7);
154 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x8, apicid_sb800, 0x8);
155 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x9, apicid_sb800, 0x9);
156 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_isa, 0xa, apicid_sb800, 0xa);
157 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_isa, 0x1c, apicid_sb800, 0x13);
158 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, apicid_sb800, 0xc);
159 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, apicid_sb800, 0xd);
160 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid_sb800, 0xe);
161 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_sb800, 0xf);
163 /* PCI interrupts are level triggered, and are
164 * associated with a specific bus/device/function tuple.
166 #define PCI_INT(bus, dev, int_sign, pin) \
167 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb800, (pin))
170 PCI_INT(0x0, 0x14, 0x0, 0x10);
173 PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
176 PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
177 PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
178 PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
179 PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
180 PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
181 PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
182 PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
185 PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
186 PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
189 /* on board NIC & Slot PCIE. */
193 PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
194 PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
195 PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
196 PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
199 PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
200 PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
201 PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
202 PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
205 PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
206 PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
207 PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
208 PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
210 PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12);
211 PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13);
212 PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14);
215 PCI_INT(0x0, 0x06, 0x0, 0x13);
218 PCI_INT(0x0, 0x15, 0x0, 0x10);
220 PCI_INT(0x0, 0x15, 0x1, 0x11);
222 PCI_INT(0x0, 0x15, 0x2, 0x12);
224 PCI_INT(0x0, 0x15, 0x3, 0x13);
226 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
227 IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
228 IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
229 /* There is no extension information... */
231 /* Compute the checksums */
233 smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
234 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
235 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
236 mc, smp_next_mpe_entry(mc));
237 return smp_next_mpe_entry(mc);
240 unsigned long write_smp_table(unsigned long addr)
243 v = smp_write_floating_table(addr, 0);
244 return (unsigned long)smp_write_config_table(v);