src/mainboard/amd/inagua/fadt.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20
  21 /*
  22  * ACPI - create the Fixed ACPI Description Tables (FADT)
  23  */
  24
  25
  26 #include <string.h>
  27 #include <console/console.h>
  28 #include <arch/acpi.h>
  29 #include <arch/io.h>
  30 #include <device/device.h>
  31 #include "SBPLATFORM.h"
  32
  33 void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
  34 {
  35         u16 val = 0;
  36         acpi_header_t *header = &(fadt->header);
  37
  38         printk(BIOS_DEBUG, "ACPI_BLK_BASE: 0x%04x\n", ACPI_BLK_BASE);
  39         /* Prepare the header */
  40         memset((void *)fadt, 0, sizeof(acpi_fadt_t));
  41         memcpy(header->signature, "FACP", 4);
  42         header->length = 244;
  43         header->revision = 3;
  44         memcpy(header->oem_id, OEM_ID, 6);
  45         memcpy(header->oem_table_id, "COREBOOT", 8);
  46         memcpy(header->asl_compiler_id, ASLC, 4);
  47         header->asl_compiler_revision = 0;
  48
  49         fadt->firmware_ctrl = (u32) facs;
  50         fadt->dsdt = (u32) dsdt;
  51         /* 3=Workstation,4=Enterprise Server, 7=Performance Server */
  52         fadt->preferred_pm_profile = 0x03;
  53         fadt->sci_int = 9;
  54         /* disable system management mode by setting to 0: */
  55         fadt->smi_cmd = 0;
  56         fadt->acpi_enable = 0xf0;
  57         fadt->acpi_disable = 0xf1;
  58         fadt->s4bios_req = 0x0;
  59         fadt->pstate_cnt = 0xe2;
  60
  61         val = PM1_EVT_BLK_ADDRESS;
  62         WritePMIO(SB_PMIOA_REG60, AccWidthUint16, &val);
  63         val = PM1_CNT_BLK_ADDRESS;
  64         WritePMIO(SB_PMIOA_REG62, AccWidthUint16, &val);
  65         val = PM1_TMR_BLK_ADDRESS;
  66         WritePMIO(SB_PMIOA_REG64, AccWidthUint16, &val);
  67         val = GPE0_BLK_ADDRESS;
  68         WritePMIO(SB_PMIOA_REG68, AccWidthUint16, &val);
  69
  70         /* CpuControl is in \_PR.CPU0, 6 bytes */
  71         val = CPU_CNT_BLK_ADDRESS;
  72         WritePMIO(SB_PMIOA_REG66, AccWidthUint16, &val);
  73         val = 0;
  74         WritePMIO(SB_PMIOA_REG6A, AccWidthUint16, &val);
  75         val = ACPI_PMA_CNT_BLK_ADDRESS;
  76         WritePMIO(SB_PMIOA_REG6C, AccWidthUint16, &val);
  77
  78         /* AcpiDecodeEnable, When set, SB uses the contents of the
  79          * PM registers at index 60-6B to decode ACPI I/O address.
  80          * AcpiSmiEn & SmiCmdEn*/
  81         val = BIT0 | BIT1 | BIT2 | BIT4;
  82         WritePMIO(SB_PMIOA_REG74, AccWidthUint16, &val);
  83
  84         /* RTC_En_En, TMR_En_En, GBL_EN_EN */
  85         outl(0x1, PM1_CNT_BLK_ADDRESS);           /* set SCI_EN */
  86         fadt->pm1a_evt_blk = PM1_EVT_BLK_ADDRESS;
  87         fadt->pm1b_evt_blk = 0x0000;
  88         fadt->pm1a_cnt_blk = PM1_CNT_BLK_ADDRESS;
  89         fadt->pm1b_cnt_blk = 0x0000;
  90         fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK_ADDRESS;
  91         fadt->pm_tmr_blk = PM1_TMR_BLK_ADDRESS;
  92         fadt->gpe0_blk = GPE0_BLK_ADDRESS;
  93         fadt->gpe1_blk = 0x0000;        /* we dont have gpe1 block, do we? */
  94
  95         fadt->pm1_evt_len = 4;
  96         fadt->pm1_cnt_len = 2;
  97         fadt->pm2_cnt_len = 1;
  98         fadt->pm_tmr_len = 4;
  99         fadt->gpe0_blk_len = 8;
 100         fadt->gpe1_blk_len = 0;
 101         fadt->gpe1_base = 0;
 102
 103         fadt->cst_cnt = 0xe3;
 104         fadt->p_lvl2_lat = 101;
 105         fadt->p_lvl3_lat = 1001;
 106         fadt->flush_size = 0;
 107         fadt->flush_stride = 0;
 108         fadt->duty_offset = 1;
 109         fadt->duty_width = 3;
 110         fadt->day_alrm = 0;     /* 0x7d these have to be */
 111         fadt->mon_alrm = 0;     /* 0x7e added to cmos.layout */
 112         fadt->century = 0;      /* 0x7f to make rtc alrm work */
 113         fadt->iapc_boot_arch = 0x3;     /* See table 5-11 */
 114         fadt->flags = 0x0001c1a5;/* 0x25; */
 115
 116         fadt->res2 = 0;
 117
 118         fadt->reset_reg.space_id = 1;
 119         fadt->reset_reg.bit_width = 8;
 120         fadt->reset_reg.bit_offset = 0;
 121         fadt->reset_reg.resv = 0;
 122         fadt->reset_reg.addrl = 0xcf9;
 123         fadt->reset_reg.addrh = 0x0;
 124
 125         fadt->reset_value = 6;
 126         fadt->x_firmware_ctl_l = (u32) facs;
 127         fadt->x_firmware_ctl_h = 0;
 128         fadt->x_dsdt_l = (u32) dsdt;
 129         fadt->x_dsdt_h = 0;
 130
 131         fadt->x_pm1a_evt_blk.space_id = 1;
 132         fadt->x_pm1a_evt_blk.bit_width = 32;
 133         fadt->x_pm1a_evt_blk.bit_offset = 0;
 134         fadt->x_pm1a_evt_blk.resv = 0;
 135         fadt->x_pm1a_evt_blk.addrl = PM1_EVT_BLK_ADDRESS;
 136         fadt->x_pm1a_evt_blk.addrh = 0x0;
 137
 138         fadt->x_pm1b_evt_blk.space_id = 1;
 139         fadt->x_pm1b_evt_blk.bit_width = 4;
 140         fadt->x_pm1b_evt_blk.bit_offset = 0;
 141         fadt->x_pm1b_evt_blk.resv = 0;
 142         fadt->x_pm1b_evt_blk.addrl = 0x0;
 143         fadt->x_pm1b_evt_blk.addrh = 0x0;
 144
 145
 146         fadt->x_pm1a_cnt_blk.space_id = 1;
 147         fadt->x_pm1a_cnt_blk.bit_width = 16;
 148         fadt->x_pm1a_cnt_blk.bit_offset = 0;
 149         fadt->x_pm1a_cnt_blk.resv = 0;
 150         fadt->x_pm1a_cnt_blk.addrl = PM1_CNT_BLK_ADDRESS;
 151         fadt->x_pm1a_cnt_blk.addrh = 0x0;
 152
 153         fadt->x_pm1b_cnt_blk.space_id = 1;
 154         fadt->x_pm1b_cnt_blk.bit_width = 2;
 155         fadt->x_pm1b_cnt_blk.bit_offset = 0;
 156         fadt->x_pm1b_cnt_blk.resv = 0;
 157         fadt->x_pm1b_cnt_blk.addrl = 0x0;
 158         fadt->x_pm1b_cnt_blk.addrh = 0x0;
 159
 160
 161         fadt->x_pm2_cnt_blk.space_id = 1;
 162         fadt->x_pm2_cnt_blk.bit_width = 0;
 163         fadt->x_pm2_cnt_blk.bit_offset = 0;
 164         fadt->x_pm2_cnt_blk.resv = 0;
 165         fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK_ADDRESS;
 166         fadt->x_pm2_cnt_blk.addrh = 0x0;
 167
 168
 169         fadt->x_pm_tmr_blk.space_id = 1;
 170         fadt->x_pm_tmr_blk.bit_width = 32;
 171         fadt->x_pm_tmr_blk.bit_offset = 0;
 172         fadt->x_pm_tmr_blk.resv = 0;
 173         fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS;
 174         fadt->x_pm_tmr_blk.addrh = 0x0;
 175
 176
 177         fadt->x_gpe0_blk.space_id = 1;
 178         fadt->x_gpe0_blk.bit_width = 32;
 179         fadt->x_gpe0_blk.bit_offset = 0;
 180         fadt->x_gpe0_blk.resv = 0;
 181         fadt->x_gpe0_blk.addrl = GPE0_BLK_ADDRESS;
 182         fadt->x_gpe0_blk.addrh = 0x0;
 183
 184
 185         fadt->x_gpe1_blk.space_id = 1;
 186         fadt->x_gpe1_blk.bit_width = 0;
 187         fadt->x_gpe1_blk.bit_offset = 0;
 188         fadt->x_gpe1_blk.resv = 0;
 189         fadt->x_gpe1_blk.addrl = 0;
 190         fadt->x_gpe1_blk.addrh = 0x0;
 191
 192         header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
 193
 194 }