2 * This file is part of the coreboot project.
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 /*----------------------------------------------------------------------------------------
21 * M O D U L E S U S E D
22 *----------------------------------------------------------------------------------------
27 #include "agesawrapper.h"
28 #include "BiosCallOuts.h"
29 #include "cpuRegisters.h"
30 #include "cpuCacheInit.h"
31 #include "cpuApicUtilities.h"
32 #include "cpuEarlyInit.h"
33 #include "cpuLateInit.h"
34 #include "Dispatcher.h"
35 #include "cpuCacheInit.h"
37 #include "PlatformGnbPcieComplex.h"
40 #define FILECODE UNASSIGNED_FILE_FILECODE
42 /*----------------------------------------------------------------------------------------
43 * D E F I N I T I O N S A N D M A C R O S
44 *----------------------------------------------------------------------------------------
47 /* ACPI table pointers returned by AmdInitLate */
48 VOID *DmiTable = NULL;
49 VOID *AcpiPstate = NULL;
50 VOID *AcpiSrat = NULL;
51 VOID *AcpiSlit = NULL;
53 VOID *AcpiWheaMce = NULL;
54 VOID *AcpiWheaCmc = NULL;
55 VOID *AcpiAlib = NULL;
58 /*----------------------------------------------------------------------------------------
59 * T Y P E D E F S A N D S T R U C T U R E S
60 *----------------------------------------------------------------------------------------
63 /*----------------------------------------------------------------------------------------
64 * P R O T O T Y P E S O F L O C A L F U N C T I O N S
65 *----------------------------------------------------------------------------------------
68 /*----------------------------------------------------------------------------------------
69 * E X P O R T E D F U N C T I O N S
70 *----------------------------------------------------------------------------------------
73 /*---------------------------------------------------------------------------------------
74 * L O C A L F U N C T I O N S
75 *---------------------------------------------------------------------------------------
78 agesawrapper_amdinitcpuio (
86 AMD_CONFIG_PARAMS StdHeader;
88 /* Enable MMIO on AMD CPU Address Map Controller */
90 /* Start to set MMIO 0000A0000-0000BFFFF to Node0 Link0 */
91 PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
93 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
94 PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
96 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
98 /* Set TOM-DFFFFFFF to Node0 Link0. */
99 PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
100 PciData = 0x00DFFF00;
101 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
102 LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
103 MsrReg = (MsrReg >> 8) | 3;
104 PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
105 PciData = (UINT32)MsrReg;
106 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
107 /* Set E0000000-FFFFFFFF to Node0 Link0 with NP set. */
108 PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xBC);
109 PciData = 0x00FFFF00 | 0x80;
110 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
111 PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xB8);
112 PciData = (PCIE_BASE_ADDRESS >> 8) | 03;
113 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
114 /* Start to set PCIIO 0000-FFFF to Node0 Link0 with ISA&VGA set. */
115 PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
116 PciData = 0x0000F000;
117 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
118 PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
119 PciData = 0x00000013;
120 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
121 Status = AGESA_SUCCESS;
122 return (UINT32)Status;
126 agesawrapper_amdinitmmio (
134 AMD_CONFIG_PARAMS StdHeader;
137 Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
138 Address MSR register.
140 MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (8 << 2) | 1;
141 LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
144 Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
146 LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
147 MsrReg = MsrReg | 0x0000400000000000;
148 LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
150 /* Set Ontario Link Data */
151 PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0);
152 PciData = 0x01308002;
153 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
154 PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4);
155 PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;
156 LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
159 /* Set ROM cache onto WP to decrease post time */
160 MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5;
161 LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
162 MsrReg = (0x1000000000 - CONFIG_ROM_SIZE) | 0x800;
163 LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
165 Status = AGESA_SUCCESS;
166 return (UINT32)Status;
170 agesawrapper_amdinitreset (
175 AMD_INTERFACE_PARAMS AmdParamStruct;
176 AMD_RESET_PARAMS AmdResetParams;
178 LibAmdMemFill (&AmdParamStruct,
180 sizeof (AMD_INTERFACE_PARAMS),
181 &(AmdParamStruct.StdHeader));
184 LibAmdMemFill (&AmdResetParams,
186 sizeof (AMD_RESET_PARAMS),
187 &(AmdResetParams.StdHeader));
189 AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
190 AmdParamStruct.AllocationMethod = ByHost;
191 AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
192 AmdParamStruct.NewStructPtr = &AmdResetParams;
193 AmdParamStruct.StdHeader.AltImageBasePtr = 0;
194 AmdParamStruct.StdHeader.CalloutPtr = NULL;
195 AmdParamStruct.StdHeader.Func = 0;
196 AmdParamStruct.StdHeader.ImageBasePtr = 0;
197 AmdCreateStruct (&AmdParamStruct);
198 AmdResetParams.HtConfig.Depth = 0;
200 status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
201 if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
202 AmdReleaseStruct (&AmdParamStruct);
203 return (UINT32)status;
207 agesawrapper_amdinitearly (
212 AMD_INTERFACE_PARAMS AmdParamStruct;
213 AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
215 LibAmdMemFill (&AmdParamStruct,
217 sizeof (AMD_INTERFACE_PARAMS),
218 &(AmdParamStruct.StdHeader));
220 AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
221 AmdParamStruct.AllocationMethod = PreMemHeap;
222 AmdParamStruct.StdHeader.AltImageBasePtr = 0;
223 AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
224 AmdParamStruct.StdHeader.Func = 0;
225 AmdParamStruct.StdHeader.ImageBasePtr = 0;
226 AmdCreateStruct (&AmdParamStruct);
228 AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
229 OemCustomizeInitEarly (AmdEarlyParamsPtr);
231 status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
232 if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
233 AmdReleaseStruct (&AmdParamStruct);
235 return (UINT32)status;
239 agesawrapper_amdinitpost (
246 AMD_INTERFACE_PARAMS AmdParamStruct;
247 BIOS_HEAP_MANAGER *BiosManagerPtr;
249 LibAmdMemFill (&AmdParamStruct,
251 sizeof (AMD_INTERFACE_PARAMS),
252 &(AmdParamStruct.StdHeader));
254 AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
255 AmdParamStruct.AllocationMethod = PreMemHeap;
256 AmdParamStruct.StdHeader.AltImageBasePtr = 0;
257 AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
258 AmdParamStruct.StdHeader.Func = 0;
259 AmdParamStruct.StdHeader.ImageBasePtr = 0;
261 AmdCreateStruct (&AmdParamStruct);
262 status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr);
263 if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
264 AmdReleaseStruct (&AmdParamStruct);
265 /* Initialize heap space */
266 BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS;
268 HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER));
269 for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++)
271 *HeadPtr = 0x00000000;
274 BiosManagerPtr->StartOfAllocatedNodes = 0;
275 BiosManagerPtr->StartOfFreedNodes = 0;
277 return (UINT32)status;
281 agesawrapper_amdinitenv (
286 AMD_INTERFACE_PARAMS AmdParamStruct;
290 LibAmdMemFill (&AmdParamStruct,
292 sizeof (AMD_INTERFACE_PARAMS),
293 &(AmdParamStruct.StdHeader));
295 AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
296 AmdParamStruct.AllocationMethod = PostMemDram;
297 AmdParamStruct.StdHeader.AltImageBasePtr = 0;
298 AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
299 AmdParamStruct.StdHeader.Func = 0;
300 AmdParamStruct.StdHeader.ImageBasePtr = 0;
301 AmdCreateStruct (&AmdParamStruct);
302 status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr);
303 if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
304 /* Initialize Subordinate Bus Number and Secondary Bus Number
305 * In platform BIOS this address is allocated by PCI enumeration code
308 PciAddress.Address.Bus = 0;
309 PciAddress.Address.Device = 1;
310 PciAddress.Address.Function = 0;
311 PciAddress.Address.Register = 0x18;
312 /* Write to D1F0x18 */
313 LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
314 PciValue |= 0x00010100;
315 LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
317 /* Initialize GMM Base Address for Legacy Bridge Mode
320 PciAddress.Address.Bus = 1;
321 PciAddress.Address.Device = 5;
322 PciAddress.Address.Function = 0;
323 PciAddress.Address.Register = 0x18;
325 LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
326 PciValue |= 0x96000000;
327 LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
329 /* Initialize FB Base Address for Legacy Bridge Mode
332 PciAddress.Address.Register = 0x10;
333 LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
334 PciValue |= 0x80000000;
335 LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
337 /* Initialize GMM Base Address for Pcie Mode
340 PciAddress.Address.Bus = 0;
341 PciAddress.Address.Device = 1;
342 PciAddress.Address.Function = 0;
343 PciAddress.Address.Register = 0x18;
345 LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
346 PciValue |= 0x96000000;
347 LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
349 /* Initialize FB Base Address for Pcie Mode
352 PciAddress.Address.Register = 0x10;
353 LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
354 PciValue |= 0x80000000;
355 LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
358 /* Initialize MMIO Base and Limit Address
361 PciAddress.Address.Bus = 0;
362 PciAddress.Address.Device = 1;
363 PciAddress.Address.Function = 0;
364 PciAddress.Address.Register = 0x20;
366 LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
367 PciValue |= 0x96009600;
368 LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
370 /* Initialize MMIO Prefetchable Memory Limit and Base
373 PciAddress.Address.Register = 0x24;
374 LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
375 PciValue |= 0x8FF18001;
376 LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
377 AmdReleaseStruct (&AmdParamStruct);
379 return (UINT32)status;
383 agesawrapper_getlateinitptr (
411 agesawrapper_amdinitmid (
416 AMD_INTERFACE_PARAMS AmdParamStruct;
418 /* Enable MMIO on AMD CPU Address Map Controller */
419 agesawrapper_amdinitcpuio ();
421 LibAmdMemFill (&AmdParamStruct,
423 sizeof (AMD_INTERFACE_PARAMS),
424 &(AmdParamStruct.StdHeader));
426 AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
427 AmdParamStruct.AllocationMethod = PostMemDram;
428 AmdParamStruct.StdHeader.AltImageBasePtr = 0;
429 AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
430 AmdParamStruct.StdHeader.Func = 0;
431 AmdParamStruct.StdHeader.ImageBasePtr = 0;
433 AmdCreateStruct (&AmdParamStruct);
435 status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
436 if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
437 AmdReleaseStruct (&AmdParamStruct);
439 return (UINT32)status;
443 agesawrapper_amdinitlate (
448 AMD_LATE_PARAMS AmdLateParams;
450 LibAmdMemFill (&AmdLateParams,
452 sizeof (AMD_LATE_PARAMS),
453 &(AmdLateParams.StdHeader));
455 AmdLateParams.StdHeader.AltImageBasePtr = 0;
456 AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
457 AmdLateParams.StdHeader.Func = 0;
458 AmdLateParams.StdHeader.ImageBasePtr = 0;
460 Status = AmdInitLate (&AmdLateParams);
461 if (Status != AGESA_SUCCESS) {
462 agesawrapper_amdreadeventlog();
463 ASSERT(Status == AGESA_SUCCESS);
466 DmiTable = AmdLateParams.DmiTable;
467 AcpiPstate = AmdLateParams.AcpiPState;
468 AcpiSrat = AmdLateParams.AcpiSrat;
469 AcpiSlit = AmdLateParams.AcpiSlit;
471 AcpiWheaMce = AmdLateParams.AcpiWheaMce;
472 AcpiWheaCmc = AmdLateParams.AcpiWheaCmc;
473 AcpiAlib = AmdLateParams.AcpiAlib;
475 return (UINT32)Status;
479 agesawrapper_amdlaterunaptask (
485 AMD_LATE_PARAMS AmdLateParams;
487 LibAmdMemFill (&AmdLateParams,
489 sizeof (AMD_LATE_PARAMS),
490 &(AmdLateParams.StdHeader));
492 AmdLateParams.StdHeader.AltImageBasePtr = 0;
493 AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
494 AmdLateParams.StdHeader.Func = 0;
495 AmdLateParams.StdHeader.ImageBasePtr = 0;
497 Status = AmdLateRunApTask (&AmdLateParams);
498 if (Status != AGESA_SUCCESS) {
499 agesawrapper_amdreadeventlog();
500 ASSERT(Status == AGESA_SUCCESS);
503 DmiTable = AmdLateParams.DmiTable;
504 AcpiPstate = AmdLateParams.AcpiPState;
505 AcpiSrat = AmdLateParams.AcpiSrat;
506 AcpiSlit = AmdLateParams.AcpiSlit;
508 AcpiWheaMce = AmdLateParams.AcpiWheaMce;
509 AcpiWheaCmc = AmdLateParams.AcpiWheaCmc;
510 AcpiAlib = AmdLateParams.AcpiAlib;
512 return (UINT32)Status;
516 agesawrapper_amdreadeventlog (
521 EVENT_PARAMS AmdEventParams;
523 LibAmdMemFill (&AmdEventParams,
525 sizeof (EVENT_PARAMS),
526 &(AmdEventParams.StdHeader));
528 AmdEventParams.StdHeader.AltImageBasePtr = 0;
529 AmdEventParams.StdHeader.CalloutPtr = NULL;
530 AmdEventParams.StdHeader.Func = 0;
531 AmdEventParams.StdHeader.ImageBasePtr = 0;
532 Status = AmdReadEventLog (&AmdEventParams);
533 while (AmdEventParams.EventClass != 0) {
534 printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo);
535 printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2);
536 printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4);
537 Status = AmdReadEventLog (&AmdEventParams);
540 return (UINT32)Status;