src/mainboard/amd/inagua/agesawrapper.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 /*-----------------------------------------------------------------------------
  21  *                                              M O D U L E S           U S E D
  22  *-----------------------------------------------------------------------------
  23  */
  24
  25 #include <stdint.h>
  26 #include <string.h>
  27 #include "agesawrapper.h"
  28 #include "BiosCallOuts.h"
  29 #include "cpuRegisters.h"
  30 #include "cpuCacheInit.h"
  31 #include "cpuApicUtilities.h"
  32 #include "cpuEarlyInit.h"
  33 #include "cpuLateInit.h"
  34 #include "Dispatcher.h"
  35 #include "cpuCacheInit.h"
  36 #include "amdlib.h"
  37 #include "PlatformGnbPcieComplex.h"
  38 #include "Filecode.h"
  39
  40 #define FILECODE UNASSIGNED_FILE_FILECODE
  41
  42 /*------------------------------------------------------------------------------
  43  *                                      D E F I N I T I O N S           A N D           M A C R O S
  44  *------------------------------------------------------------------------------
  45  */
  46
  47 /* ACPI table pointers returned by AmdInitLate */
  48 VOID *DmiTable          = NULL;
  49 VOID *AcpiPstate        = NULL;
  50 VOID *AcpiSrat          = NULL;
  51 VOID *AcpiSlit          = NULL;
  52
  53 VOID *AcpiWheaMce       = NULL;
  54 VOID *AcpiWheaCmc       = NULL;
  55 VOID *AcpiAlib          = NULL;
  56
  57
  58 /*------------------------------------------------------------------------------
  59  *                              T Y P E D E F S          A N D           S T R U C T U R E S
  60  *------------------------------------------------------------------------------
  61  */
  62
  63 /*------------------------------------------------------------------------------
  64  *      P R O T O T Y P E S              O F             L O C A L               F U N C T I O N S
  65  *------------------------------------------------------------------------------
  66  */
  67
  68 /*------------------------------------------------------------------------------
  69  *                                              E X P O R T E D         F U N C T I O N S
  70  *------------------------------------------------------------------------------
  71  */
  72
  73 /*------------------------------------------------------------------------------
  74  *                                              L O C A L               F U N C T I O N S
  75  *------------------------------------------------------------------------------
  76  */
  77 UINT32
  78 agesawrapper_amdinitcpuio (
  79         VOID
  80         )
  81 {
  82         AGESA_STATUS            Status;
  83         UINT64                          MsrReg;
  84         UINT32                          PciData;
  85         PCI_ADDR                        PciAddress;
  86         AMD_CONFIG_PARAMS       StdHeader;
  87
  88         /* Enable MMIO on AMD CPU Address Map Controller */
  89
  90         /* Start to set MMIO 0000A0000-0000BFFFF to Node0 Link0 */
  91         PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
  92         PciData = 0x00000B00;
  93         LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
  94         PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
  95         PciData = 0x00000A03;
  96         LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
  97
  98         /* Set TOM-DFFFFFFF to Node0 Link0. */
  99         PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
 100         PciData = 0x00DFFF00;
 101         LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 102         LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
 103         MsrReg = (MsrReg >> 8) | 3;
 104         PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
 105         PciData = (UINT32)MsrReg;
 106         LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 107         /* Set E0000000-FFFFFFFF to Node0 Link0 with NP set. */
 108         PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xBC);
 109         PciData = 0x00FFFF00 | 0x80;
 110         LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 111         PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xB8);
 112         PciData = (PCIE_BASE_ADDRESS >> 8) | 03;
 113         LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 114         /* Start to set PCIIO 0000-FFFF to Node0 Link0 with ISA&VGA set. */
 115         PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
 116         PciData = 0x0000F000;
 117         LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 118         PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
 119         PciData = 0x00000013;
 120         LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 121         Status = AGESA_SUCCESS;
 122         return (UINT32)Status;
 123 }
 124
 125 UINT32
 126 agesawrapper_amdinitmmio (
 127         VOID
 128         )
 129 {
 130         AGESA_STATUS            Status;
 131         UINT64                          MsrReg;
 132         UINT32                          PciData;
 133         PCI_ADDR                        PciAddress;
 134         AMD_CONFIG_PARAMS       StdHeader;
 135
 136         /*
 137          Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
 138          Address MSR register.
 139         */
 140         MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (8 << 2) | 1;
 141         LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
 142
 143         /*
 144          Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
 145         */
 146         LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
 147         MsrReg = MsrReg | 0x0000400000000000;
 148         LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
 149
 150         /* Set Ontario Link Data */
 151         PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0);
 152         PciData = 0x01308002;
 153         LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 154         PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4);
 155         PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;
 156         LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 157
 158
 159         /* Set ROM cache onto WP to decrease post time */
 160         MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5;
 161         LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
 162         MsrReg = (0x1000000000 - CONFIG_ROM_SIZE) | 0x800;
 163         LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
 164
 165         Status = AGESA_SUCCESS;
 166         return (UINT32)Status;
 167 }
 168
 169 UINT32
 170 agesawrapper_amdinitreset (
 171         VOID
 172         )
 173 {
 174         AGESA_STATUS status;
 175         AMD_INTERFACE_PARAMS AmdParamStruct;
 176         AMD_RESET_PARAMS AmdResetParams;
 177
 178         LibAmdMemFill (&AmdParamStruct,
 179                                         0,
 180                                         sizeof (AMD_INTERFACE_PARAMS),
 181                                         &(AmdParamStruct.StdHeader));
 182
 183
 184         LibAmdMemFill (&AmdResetParams,
 185                                         0,
 186                                         sizeof (AMD_RESET_PARAMS),
 187                                         &(AmdResetParams.StdHeader));
 188
 189         AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
 190         AmdParamStruct.AllocationMethod = ByHost;
 191         AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
 192         AmdParamStruct.NewStructPtr = &AmdResetParams;
 193         AmdParamStruct.StdHeader.AltImageBasePtr = 0;
 194         AmdParamStruct.StdHeader.CalloutPtr = NULL;
 195         AmdParamStruct.StdHeader.Func = 0;
 196         AmdParamStruct.StdHeader.ImageBasePtr = 0;
 197         AmdCreateStruct (&AmdParamStruct);
 198         AmdResetParams.HtConfig.Depth = 0;
 199
 200         status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
 201         if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
 202         AmdReleaseStruct (&AmdParamStruct);
 203         return (UINT32)status;
 204  }
 205
 206 UINT32
 207 agesawrapper_amdinitearly (
 208         VOID
 209         )
 210 {
 211         AGESA_STATUS status;
 212         AMD_INTERFACE_PARAMS AmdParamStruct;
 213         AMD_EARLY_PARAMS         *AmdEarlyParamsPtr;
 214
 215         LibAmdMemFill (&AmdParamStruct,
 216                                         0,
 217                                         sizeof (AMD_INTERFACE_PARAMS),
 218                                         &(AmdParamStruct.StdHeader));
 219
 220         AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
 221         AmdParamStruct.AllocationMethod = PreMemHeap;
 222         AmdParamStruct.StdHeader.AltImageBasePtr = 0;
 223         AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
 224         AmdParamStruct.StdHeader.Func = 0;
 225         AmdParamStruct.StdHeader.ImageBasePtr = 0;
 226         AmdCreateStruct (&AmdParamStruct);
 227
 228         AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
 229         OemCustomizeInitEarly (AmdEarlyParamsPtr);
 230
 231         status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
 232         if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
 233         AmdReleaseStruct (&AmdParamStruct);
 234
 235         return (UINT32)status;
 236 }
 237
 238 UINT32
 239 agesawrapper_amdinitpost (
 240         VOID
 241         )
 242 {
 243         AGESA_STATUS status;
 244         UINT16                                  i;
 245         UINT32                                  *HeadPtr;
 246         AMD_INTERFACE_PARAMS    AmdParamStruct;
 247         BIOS_HEAP_MANAGER               *BiosManagerPtr;
 248
 249         LibAmdMemFill (&AmdParamStruct,
 250                                         0,
 251                                         sizeof (AMD_INTERFACE_PARAMS),
 252                                         &(AmdParamStruct.StdHeader));
 253
 254         AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
 255         AmdParamStruct.AllocationMethod = PreMemHeap;
 256         AmdParamStruct.StdHeader.AltImageBasePtr = 0;
 257         AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
 258         AmdParamStruct.StdHeader.Func = 0;
 259         AmdParamStruct.StdHeader.ImageBasePtr = 0;
 260
 261         AmdCreateStruct (&AmdParamStruct);
 262         status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr);
 263         if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
 264         AmdReleaseStruct (&AmdParamStruct);
 265         /* Initialize heap space */
 266         BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS;
 267
 268         HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER));
 269         for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++)
 270         {
 271                 *HeadPtr = 0x00000000;
 272                 HeadPtr++;
 273         }
 274         BiosManagerPtr->StartOfAllocatedNodes = 0;
 275         BiosManagerPtr->StartOfFreedNodes = 0;
 276
 277         return (UINT32)status;
 278 }
 279
 280 UINT32
 281 agesawrapper_amdinitenv (
 282         VOID
 283         )
 284 {
 285         AGESA_STATUS status;
 286         AMD_INTERFACE_PARAMS AmdParamStruct;
 287         PCI_ADDR                         PciAddress;
 288         UINT32                           PciValue;
 289
 290         LibAmdMemFill (&AmdParamStruct,
 291                                         0,
 292                                         sizeof (AMD_INTERFACE_PARAMS),
 293                                         &(AmdParamStruct.StdHeader));
 294
 295         AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
 296         AmdParamStruct.AllocationMethod = PostMemDram;
 297         AmdParamStruct.StdHeader.AltImageBasePtr = 0;
 298         AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
 299         AmdParamStruct.StdHeader.Func = 0;
 300         AmdParamStruct.StdHeader.ImageBasePtr = 0;
 301         AmdCreateStruct (&AmdParamStruct);
 302         status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr);
 303         if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
 304         /* Initialize Subordinate Bus Number and Secondary Bus Number
 305          * In platform BIOS this address is allocated by PCI enumeration code
 306                  Modify D1F0x18
 307          */
 308         PciAddress.Address.Bus = 0;
 309         PciAddress.Address.Device = 1;
 310         PciAddress.Address.Function = 0;
 311         PciAddress.Address.Register = 0x18;
 312         /* Write to D1F0x18 */
 313         LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
 314         PciValue |= 0x00010100;
 315         LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
 316
 317         /* Initialize GMM Base Address for Legacy Bridge Mode
 318         *       Modify B1D5F0x18
 319         */
 320         PciAddress.Address.Bus = 1;
 321         PciAddress.Address.Device = 5;
 322         PciAddress.Address.Function = 0;
 323         PciAddress.Address.Register = 0x18;
 324
 325         LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
 326         PciValue |= 0x96000000;
 327         LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
 328
 329         /* Initialize FB Base Address for Legacy Bridge Mode
 330         * Modify B1D5F0x10
 331         */
 332         PciAddress.Address.Register = 0x10;
 333         LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
 334         PciValue |= 0x80000000;
 335         LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
 336
 337         /* Initialize GMM Base Address for Pcie Mode
 338         *       Modify B0D1F0x18
 339         */
 340         PciAddress.Address.Bus = 0;
 341         PciAddress.Address.Device = 1;
 342         PciAddress.Address.Function = 0;
 343         PciAddress.Address.Register = 0x18;
 344
 345         LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
 346         PciValue |= 0x96000000;
 347         LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
 348
 349         /* Initialize FB Base Address for Pcie Mode
 350         *       Modify B0D1F0x10
 351         */
 352         PciAddress.Address.Register = 0x10;
 353         LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
 354         PciValue |= 0x80000000;
 355         LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
 356
 357
 358         /* Initialize MMIO Base and Limit Address
 359         *       Modify B0D1F0x20
 360         */
 361         PciAddress.Address.Bus = 0;
 362         PciAddress.Address.Device = 1;
 363         PciAddress.Address.Function = 0;
 364         PciAddress.Address.Register = 0x20;
 365
 366         LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
 367         PciValue |= 0x96009600;
 368         LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
 369
 370         /* Initialize MMIO Prefetchable Memory Limit and Base
 371         *       Modify B0D1F0x24
 372         */
 373         PciAddress.Address.Register = 0x24;
 374         LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
 375         PciValue |= 0x8FF18001;
 376         LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
 377         AmdReleaseStruct (&AmdParamStruct);
 378
 379         return (UINT32)status;
 380 }
 381
 382 VOID *
 383 agesawrapper_getlateinitptr (
 384         int pick
 385         )
 386 {
 387         switch (pick) {
 388                 case PICK_DMI:
 389                         return DmiTable;
 390                 case PICK_PSTATE:
 391                         return AcpiPstate;
 392                 case PICK_SRAT:
 393                         return AcpiSrat;
 394                 case PICK_SLIT:
 395                         return AcpiSlit;
 396                 case PICK_WHEA_MCE:
 397                         return AcpiWheaMce;
 398                 case PICK_WHEA_CMC:
 399                         return AcpiWheaCmc;
 400                 case PICK_ALIB:
 401                         return AcpiAlib;
 402                 default:
 403                         return NULL;
 404         }
 405 }
 406
 407 UINT32
 408 agesawrapper_amdinitmid (
 409         VOID
 410         )
 411 {
 412         AGESA_STATUS status;
 413         AMD_INTERFACE_PARAMS AmdParamStruct;
 414
 415         /* Enable MMIO on AMD CPU Address Map Controller */
 416         agesawrapper_amdinitcpuio ();
 417
 418         LibAmdMemFill (&AmdParamStruct,
 419                                         0,
 420                                         sizeof (AMD_INTERFACE_PARAMS),
 421                                         &(AmdParamStruct.StdHeader));
 422
 423         AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
 424         AmdParamStruct.AllocationMethod = PostMemDram;
 425         AmdParamStruct.StdHeader.AltImageBasePtr = 0;
 426         AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
 427         AmdParamStruct.StdHeader.Func = 0;
 428         AmdParamStruct.StdHeader.ImageBasePtr = 0;
 429
 430         AmdCreateStruct (&AmdParamStruct);
 431
 432         status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
 433         if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
 434         AmdReleaseStruct (&AmdParamStruct);
 435
 436         return (UINT32)status;
 437 }
 438
 439 UINT32
 440 agesawrapper_amdinitlate (
 441         VOID
 442         )
 443 {
 444         AGESA_STATUS Status;
 445         AMD_LATE_PARAMS AmdLateParams;
 446
 447         LibAmdMemFill (&AmdLateParams,
 448                                         0,
 449                                         sizeof (AMD_LATE_PARAMS),
 450                                         &(AmdLateParams.StdHeader));
 451
 452         AmdLateParams.StdHeader.AltImageBasePtr = 0;
 453         AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
 454         AmdLateParams.StdHeader.Func = 0;
 455         AmdLateParams.StdHeader.ImageBasePtr = 0;
 456
 457         Status = AmdInitLate (&AmdLateParams);
 458         if (Status != AGESA_SUCCESS) {
 459                 agesawrapper_amdreadeventlog();
 460                 ASSERT(Status == AGESA_SUCCESS);
 461         }
 462
 463         DmiTable                = AmdLateParams.DmiTable;
 464         AcpiPstate              = AmdLateParams.AcpiPState;
 465         AcpiSrat                = AmdLateParams.AcpiSrat;
 466         AcpiSlit                = AmdLateParams.AcpiSlit;
 467         AcpiWheaMce             = AmdLateParams.AcpiWheaMce;
 468         AcpiWheaCmc             = AmdLateParams.AcpiWheaCmc;
 469         AcpiAlib                = AmdLateParams.AcpiAlib;
 470
 471         return (UINT32)Status;
 472 }
 473
 474 UINT32
 475 agesawrapper_amdlaterunaptask (
 476         UINT32 Data,
 477         VOID *ConfigPtr
 478         )
 479 {
 480         AGESA_STATUS Status;
 481         AMD_LATE_PARAMS AmdLateParams;
 482
 483         LibAmdMemFill (&AmdLateParams,
 484                                         0,
 485                                         sizeof (AMD_LATE_PARAMS),
 486                                         &(AmdLateParams.StdHeader));
 487
 488         AmdLateParams.StdHeader.AltImageBasePtr = 0;
 489         AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
 490         AmdLateParams.StdHeader.Func = 0;
 491         AmdLateParams.StdHeader.ImageBasePtr = 0;
 492
 493         Status = AmdLateRunApTask (&AmdLateParams);
 494         if (Status != AGESA_SUCCESS) {
 495                 agesawrapper_amdreadeventlog();
 496                 ASSERT(Status == AGESA_SUCCESS);
 497         }
 498
 499         DmiTable                = AmdLateParams.DmiTable;
 500         AcpiPstate              = AmdLateParams.AcpiPState;
 501         AcpiSrat                = AmdLateParams.AcpiSrat;
 502         AcpiSlit                = AmdLateParams.AcpiSlit;
 503         AcpiWheaMce             = AmdLateParams.AcpiWheaMce;
 504         AcpiWheaCmc             = AmdLateParams.AcpiWheaCmc;
 505         AcpiAlib                = AmdLateParams.AcpiAlib;
 506
 507         return (UINT32)Status;
 508 }
 509
 510 UINT32
 511 agesawrapper_amdreadeventlog (
 512         VOID
 513         )
 514 {
 515         AGESA_STATUS Status;
 516         EVENT_PARAMS AmdEventParams;
 517
 518         LibAmdMemFill (&AmdEventParams,
 519                                         0,
 520                                         sizeof (EVENT_PARAMS),
 521                                         &(AmdEventParams.StdHeader));
 522
 523         AmdEventParams.StdHeader.AltImageBasePtr = 0;
 524         AmdEventParams.StdHeader.CalloutPtr = NULL;
 525         AmdEventParams.StdHeader.Func = 0;
 526         AmdEventParams.StdHeader.ImageBasePtr = 0;
 527         Status = AmdReadEventLog (&AmdEventParams);
 528         while (AmdEventParams.EventClass != 0) {
 529                 printk(BIOS_DEBUG,"\nEventLog:  EventClass = %x, EventInfo = %x.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo);
 530                 printk(BIOS_DEBUG,"     Param1 = %x, Param2 = %x.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2);
 531                 printk(BIOS_DEBUG,"     Param3 = %x, Param4 = %x.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4);
 532                 Status = AmdReadEventLog (&AmdEventParams);
 533         }
 534
 535         return (UINT32)Status;
 536 }