src/mainboard/amd/dinar/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2012 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 #include <stdint.h>
  21 #include <string.h>
  22 #include <device/pci_def.h>
  23 #include <device/pci_ids.h>
  24 #include <arch/io.h>
  25 #include <arch/stages.h>
  26 #include <device/pnp_def.h>
  27 #include <arch/romcc_io.h>
  28 #include <cpu/x86/lapic.h>
  29 #include <console/console.h>
  30 #include <console/loglevel.h>
  31 #include "cpu/x86/bist.h"
  32 #include "superio/smsc/sch4037/sch4037_early_init.c"
  33 #include "superio/smsc/sio1036/sio1036_early_init.c"
  34 #include "cpu/x86/lapic/boot_cpu.c"
  35 #include "pc80/i8254.c"
  36 #include "pc80/i8259.c"
  37 #include "nb_cimx.h"
  38 #include "sb_cimx.h"
  39 #include "Platform.h"
  40 #include <arch/cpu.h>
  41
  42 #define SERIAL_DEV PNP_DEV(CONFIG_SIO_PORT, SMSCSUPERIO_SP1)
  43
  44 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
  45 u32 agesawrapper_amdinitmmio (void);
  46 u32 agesawrapper_amdinitreset (void);
  47 u32 agesawrapper_amdinitearly (void);
  48 u32 agesawrapper_amdinitenv (void);
  49 u32 agesawrapper_amdinitlate (void);
  50 u32 agesawrapper_amdinitpost (void);
  51 u32 agesawrapper_amdinitmid (void);
  52
  53
  54
  55 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  56 {
  57         u32 val;
  58
  59         if (!cpu_init_detectedx && boot_cpu()) {
  60
  61                 post_code(0x30);
  62
  63                 sch4037_early_init (CONFIG_SIO_PORT);
  64
  65                 /* Detect SMSC SIO1036 LPC Debug Card status */
  66                 if (detect_sio1036_chip(0x4E)) {
  67                         /* Found SMSC SIO1036 LPC Debug Card */
  68                         sio1036_early_init(0x4E);
  69                 }
  70
  71                 post_code(0x31);
  72                 uart_init();
  73                 console_init();
  74
  75                 /*
  76                  * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR,
  77                  * Disable all Pcie Bridges to work around It.
  78                  */
  79                 sr56x0_rd890_disable_pcie_bridge();
  80
  81         }
  82
  83         post_code(0x32);
  84         val = agesawrapper_amdinitmmio();
  85         if (val) {
  86                 printk(BIOS_DEBUG, "agesawrapper_amdinitmmio failed: %x \n", val);
  87         } else {
  88                 printk(BIOS_DEBUG, "agesawrapper_amdinitmmio passed\n");
  89         }
  90
  91         /* Halt if there was a built in self test failure */
  92         post_code(0x33);
  93         report_bist_failure(bist);
  94
  95         // Load MPB
  96         val = cpuid_eax(1);
  97         printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
  98         printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
  99
 100         if(boot_cpu()) {
 101                 post_code(0x34);
 102                 sb_Poweron_Init();
 103         }
 104
 105         post_code(0x35);
 106         val = agesawrapper_amdinitreset();
 107         if (val) {
 108                 printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val);
 109         } else {
 110                 printk(BIOS_DEBUG, "agesawrapper_amdinitreset passed\n");
 111         }
 112
 113         post_code(0x36);
 114         val = agesawrapper_amdinitearly ();
 115         if (val) {
 116                 printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val);
 117         } else {
 118                 printk(BIOS_DEBUG, "agesawrapper_amdinitearly passed\n");
 119         }
 120
 121         post_code(0x37);
 122         nb_Poweron_Init();
 123         post_code(0x38);
 124         nb_Ht_Init();
 125
 126
 127         post_code(0x39);
 128         val = agesawrapper_amdinitpost ();
 129         if (val) {
 130                 printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val);
 131         } else {
 132                 printk(BIOS_DEBUG, "agesawrapper_amdinitpost passed\n");
 133         }
 134
 135         post_code(0x40);
 136         val = agesawrapper_amdinitenv ();
 137         if (val) {
 138                 printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val);
 139         } else {
 140                 printk(BIOS_DEBUG, "agesawrapper_amdinitenv passed\n");
 141         }
 142
 143
 144         /* Initialize i8259 pic */
 145         post_code(0x41);
 146         setup_i8259 ();
 147
 148         /* Initialize i8254 timers */
 149         post_code(0x42);
 150         setup_i8254 ();
 151
 152         post_code(0x43);
 153         print_debug("Disabling cache as ram ");
 154         disable_cache_as_ram();
 155         print_debug("done\n");
 156
 157         post_code(0x44);
 158         copy_and_run(0);
 159
 160         post_code(0x45);  // Should never see this post code.
 161 }
 162