2 * This file is part of the coreboot project.
4 * Copyright (C) 2012 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <console/console.h>
22 #include <arch/smp/mpspec.h>
23 #include <device/pci.h>
28 #include <cpu/x86/lapic.h>
30 extern u8 bus_rd890[14];
31 extern u8 bus_sb700[2];
32 extern u32 bus_type[256];
33 extern u32 sbdn_rd890;
34 extern u32 sbdn_sb700;
37 static void *smp_write_config_table(void *v)
39 struct mp_config_table *mc;
46 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
47 mptable_init(mc, LAPIC_ADDR);
49 smp_write_processors(mc);
51 mptable_write_buses(mc, NULL, &bus_isa);
54 * AGESA v5 Apply apic enumeration rules
55 * For systems with >= 16 APICs, put the IO-APICs at 0..n and
56 * put the local-APICs at m..z
57 * For systems with < 16 APICs, put the Local-APICs at 0..n and
58 * put the IO-APICs at (n + 1)..z
60 #if CONFIG_MAX_CPUS >= 16
63 apicid_sb700 = CONFIG_MAX_CPUS + 1
65 apicid_rd890 = apicid_sb700 + 1;
67 //bus_sb700[0], TODO: why bus_sb700[0] use same value of bus_rd890[0] assigned by get_pci1234(), instead of 0.
68 dev = dev_find_slot(0, PCI_DEVFN(sbdn_sb700 + 0x14, 0));
70 /* Set sb700 IOAPIC ID */
71 dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
72 smp_write_ioapic(mc, apicid_sb700, 0x20, dword);
75 * 00:12.0: PROG SATA : INT F
83 * 00:14.2: Prog HDA : INT E
88 /* Set RS5650 IOAPIC ID */
89 dev = dev_find_slot(0, PCI_DEVFN(0, 0));
91 pci_write_config32(dev, 0xF8, 0x1);
92 dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
93 smp_write_ioapic(mc, apicid_rd890, 0x20, dword);
98 /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
99 #define IO_LOCAL_INT(type, intr, apicid, pin) \
100 smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
102 mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0);
104 /* PCI interrupts are level triggered, and are
105 * associated with a specific bus/device/function tuple.
107 #define PCI_INT(bus, dev, int_sign, pin) \
108 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb700, (pin))
111 //PCI_INT(0x0, 0x14, 0x0, 0x10); //not generate interrupt, 3Ch hardcoded to 0
114 PCI_INT(0x0, 0x14, 0x2, 0x10);
117 /* OHCI0, OHCI1 hard-wired to 01h, corresponding to using INTA# */
118 /* EHCI hard-wired to 02h, corresponding to using INTB# */
120 PCI_INT(0x0, 0x12, 0x0, 0x10); /* OHCI0 Port 0~2 */
121 PCI_INT(0x0, 0x12, 0x1, 0x10); /* OHCI1 Port 3~5 */
122 PCI_INT(0x0, 0x12, 0x2, 0x11); /* EHCI Port 0~5 */
125 PCI_INT(0x0, 0x13, 0x0, 0x10); /* OHCI0 Port 6~8 */
126 PCI_INT(0x0, 0x13, 0x1, 0x10); /* OHCI1 Port 9~11 */
127 PCI_INT(0x0, 0x13, 0x2, 0x11); /* EHCI Port 6~11 */
129 /* USB3 EHCI hard-wired to 03h, corresponding to using INTC# */
130 PCI_INT(0x0, 0x14, 0x5, 0x12); /* OHCI0 Port 12~13 */
133 PCI_INT(0x0, 0x11, 0x0, 0x16); //6, INTG
135 /* on board NIC & Slot PCIE. */
136 /* configuration B doesnt need dev 5,6,7 */
138 * PCI_INT(bus_rd890[0x5], 0x0, 0x0, 0x11);
139 * PCI_INT(bus_rd890[0x6], 0x0, 0x0, 0x12);
140 * PCI_INT(bus_rd890[0x7], 0x0, 0x0, 0x13);
143 //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((13)<<2)|(0)), apicid_rd890, 28); /* dev d */
144 //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_rd890[13], (((0)<<2)|(1)), apicid_rd890, 0); /* card behind dev13 */
148 PCI_INT(bus_sb700[1], 0x5, 0x0, 0x14);
149 PCI_INT(bus_sb700[1], 0x5, 0x1, 0x15);
150 PCI_INT(bus_sb700[1], 0x5, 0x2, 0x16);
151 PCI_INT(bus_sb700[1], 0x5, 0x3, 0x17);
154 PCI_INT(bus_sb700[1], 0x6, 0x0, 0x15);
155 PCI_INT(bus_sb700[1], 0x6, 0x1, 0x16);
156 PCI_INT(bus_sb700[1], 0x6, 0x2, 0x17);
157 PCI_INT(bus_sb700[1], 0x6, 0x3, 0x14);
160 PCI_INT(bus_sb700[1], 0x7, 0x0, 0x16);
161 PCI_INT(bus_sb700[1], 0x7, 0x1, 0x17);
162 PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14);
163 PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15);
166 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
167 IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
168 IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
169 /* There is no extension information... */
171 /* Compute the checksums */
172 return mptable_finalize(mc);
175 unsigned long write_smp_table(unsigned long addr)
178 v = smp_write_floating_table(addr, 0);
179 return (unsigned long)smp_write_config_table(v);