2 * This file is part of the coreboot project.
4 * Copyright (C) 2012 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
24 #include "routing.asl"
28 /* Routing is in System Bus scope */
32 /* Bus 0, Dev 0 - RS780 Host Controller */
33 /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
34 Package(){0x0001FFFF, 0, INTC, 0 },
35 Package(){0x0001FFFF, 1, INTD, 0 },
37 Package(){0x0002FFFF, 0, INTC, 0 },
38 Package(){0x0002FFFF, 1, INTD, 0 },
39 Package(){0x0002FFFF, 2, INTA, 0 },
40 Package(){0x0002FFFF, 3, INTB, 0 },
42 Package(){0x0003FFFF, 0, INTD, 0 },
43 Package(){0x0003FFFF, 1, INTA, 0 },
44 Package(){0x0003FFFF, 2, INTB, 0 },
45 Package(){0x0003FFFF, 3, INTC, 0 },
46 /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
47 Package(){0x0004FFFF, 0, INTA, 0 },
48 Package(){0x0004FFFF, 1, INTB, 0 },
49 Package(){0x0004FFFF, 2, INTC, 0 },
50 Package(){0x0004FFFF, 3, INTD, 0 },
51 /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
52 Package(){0x0005FFFF, 0, INTB, 0 },
53 Package(){0x0005FFFF, 1, INTC, 0 },
54 Package(){0x0005FFFF, 2, INTD, 0 },
55 Package(){0x0005FFFF, 3, INTA, 0 },
56 /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
57 Package(){0x0006FFFF, 0, INTC, 0 },
58 Package(){0x0006FFFF, 1, INTD, 0 },
59 Package(){0x0006FFFF, 2, INTA, 0 },
60 Package(){0x0006FFFF, 3, INTB, 0 },
61 /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
62 Package(){0x0007FFFF, 0, INTD, 0 },
63 Package(){0x0007FFFF, 1, INTA, 0 },
64 Package(){0x0007FFFF, 2, INTB, 0 },
65 Package(){0x0007FFFF, 3, INTC, 0 },
68 /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
69 Package(){0x0014FFFF, 0, INTA, 0 },
70 Package(){0x0014FFFF, 1, INTB, 0 },
71 Package(){0x0014FFFF, 2, INTC, 0 },
72 Package(){0x0014FFFF, 3, INTD, 0 },
73 /* Bus 0, Dev 18,19,22 - USB: OHCI,EHCI */
74 Package(){0x0012FFFF, 0, INTC, 0 },
75 Package(){0x0012FFFF, 1, INTB, 0 },
76 Package(){0x0013FFFF, 0, INTC, 0 },
77 Package(){0x0013FFFF, 1, INTB, 0 },
78 Package(){0x0016FFFF, 0, INTC, 0 },
79 Package(){0x0016FFFF, 1, INTB, 0 },
80 Package(){0x0010FFFF, 0, INTC, 0 },
81 Package(){0x0010FFFF, 1, INTB, 0 },
82 /* Bus 0, Dev 17 - SATA controller #2 */
83 Package(){0x0011FFFF, 0, INTD, 0 },
84 /* Bus 0, Dev 21 - PCIe Bridge for x1 PCIe Slot */
85 Package(){0x0015FFFF, 0, INTA, 0 },
86 Package(){0x0015FFFF, 1, INTB, 0 },
87 Package(){0x0015FFFF, 2, INTC, 0 },
88 Package(){0x0015FFFF, 3, INTD, 0 },
92 /* NB devices in APIC mode */
93 /* Bus 0, Dev 0 - RS780 Host Controller */
94 /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
95 Package(){0x0001FFFF, 0, 0, 18 },
96 Package(){0x0001FFFF, 1, 0, 19 },
98 Package(){0x0002FFFF, 0, 0, 18 },
99 Package(){0x0002FFFF, 1, 0, 19 },
100 Package(){0x0002FFFF, 2, 0, 16 },
101 Package(){0x0002FFFF, 3, 0, 17 },
103 Package(){0x0003FFFF, 0, 0, 19 },
104 Package(){0x0003FFFF, 1, 0, 16 },
105 Package(){0x0003FFFF, 2, 0, 17 },
106 Package(){0x0003FFFF, 3, 0, 18 },
107 /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
108 Package(){0x0004FFFF, 0, 0, 16 },
109 Package(){0x0004FFFF, 1, 0, 17 },
110 Package(){0x0004FFFF, 2, 0, 18 },
111 Package(){0x0004FFFF, 3, 0, 19 },
112 /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
113 Package(){0x0005FFFF, 0, 0, 17 },
114 Package(){0x0005FFFF, 1, 0, 18 },
115 Package(){0x0005FFFF, 2, 0, 19 },
116 Package(){0x0005FFFF, 3, 0, 16 },
117 /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
118 Package(){0x0006FFFF, 0, 0, 18 },
119 Package(){0x0006FFFF, 1, 0, 19 },
120 Package(){0x0006FFFF, 2, 0, 16 },
121 Package(){0x0006FFFF, 3, 0, 17 },
122 /* Bus 0, Dev 7 - PCIe Bridge for network card */
123 Package(){0x0007FFFF, 0, 0, 19 },
124 Package(){0x0007FFFF, 1, 0, 16 },
125 Package(){0x0007FFFF, 2, 0, 17 },
126 Package(){0x0007FFFF, 3, 0, 18 },
128 /* SB devices in APIC mode */
129 /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
130 Package(){0x0014FFFF, 0, 0, 16 },
131 Package(){0x0014FFFF, 1, 0, 17 },
132 Package(){0x0014FFFF, 2, 0, 18 },
133 Package(){0x0014FFFF, 3, 0, 19 },
134 /* Bus 0, Dev 18,19,22 - USB: OHCI,EHCI*/
135 Package(){0x0012FFFF, 0, 0, 18 },
136 Package(){0x0012FFFF, 1, 0, 17 },
137 Package(){0x0013FFFF, 0, 0, 18 },
138 Package(){0x0013FFFF, 1, 0, 17 },
139 Package(){0x0016FFFF, 0, 0, 18 },
140 Package(){0x0016FFFF, 1, 0, 17 },
141 Package(){0x0010FFFF, 0, 0, 18 },
142 Package(){0x0010FFFF, 1, 0, 17 },
143 /* Bus 0, Dev 17 - SATA controller #2 */
144 Package(){0x0011FFFF, 0, 0, 19 },
145 /* Bus 0, Dev 21 - PCIe Bridge for x1 PCIe Slot */
146 Package(){0x0015FFFF, 0, 0, 16 },
147 Package(){0x0015FFFF, 1, 0, 17 },
148 Package(){0x0015FFFF, 2, 0, 18 },
149 Package(){0x0015FFFF, 3, 0, 19 },
153 /* For Device(PBR2) PIC mode*/
154 Package(){0x0000FFFF, 0, INTC, 0 },
155 Package(){0x0000FFFF, 1, INTD, 0 },
156 Package(){0x0000FFFF, 2, INTA, 0 },
157 Package(){0x0000FFFF, 3, INTB, 0 },
160 Name(APS2, Package(){
161 /* For Device(PBR2) APIC mode*/
162 Package(){0x0000FFFF, 0, 0, 18 },
163 Package(){0x0000FFFF, 1, 0, 19 },
164 Package(){0x0000FFFF, 2, 0, 16 },
165 Package(){0x0000FFFF, 3, 0, 17 },
169 /* For Device(PBR3) PIC mode*/
170 Package(){0x0000FFFF, 0, INTD, 0 },
171 Package(){0x0000FFFF, 1, INTA, 0 },
172 Package(){0x0000FFFF, 2, INTB, 0 },
173 Package(){0x0000FFFF, 3, INTC, 0 },
176 Name(APS3, Package(){
177 /* For Device(PBR3) APIC mode*/
178 Package(){0x0000FFFF, 0, 0, 19 },
179 Package(){0x0000FFFF, 1, 0, 16 },
180 Package(){0x0000FFFF, 2, 0, 17 },
181 Package(){0x0000FFFF, 3, 0, 18 },
185 /* For Device(PBR4) PIC mode*/
186 Package(){0x0000FFFF, 0, INTA, 0 },
187 Package(){0x0000FFFF, 1, INTB, 0 },
188 Package(){0x0000FFFF, 2, INTC, 0 },
189 Package(){0x0000FFFF, 3, INTD, 0 },
192 Name(APS4, Package(){
193 /* For Device(PBR4) APIC mode*/
194 Package(){0x0000FFFF, 0, 0, 16 },
195 Package(){0x0000FFFF, 1, 0, 17 },
196 Package(){0x0000FFFF, 2, 0, 18 },
197 Package(){0x0000FFFF, 3, 0, 19 },
201 /* For Device(PBR5) PIC mode*/
202 Package(){0x0000FFFF, 0, INTB, 0 },
203 Package(){0x0000FFFF, 1, INTC, 0 },
204 Package(){0x0000FFFF, 2, INTD, 0 },
205 Package(){0x0000FFFF, 3, INTA, 0 },
208 Name(APS5, Package(){
209 /* For Device(PBR5) APIC mode*/
210 Package(){0x0000FFFF, 0, 0, 17 },
211 Package(){0x0000FFFF, 1, 0, 18 },
212 Package(){0x0000FFFF, 2, 0, 19 },
213 Package(){0x0000FFFF, 3, 0, 16 },
217 /* For Device(PBR6) PIC mode*/
218 Package(){0x0000FFFF, 0, INTC, 0 },
219 Package(){0x0000FFFF, 1, INTD, 0 },
220 Package(){0x0000FFFF, 2, INTA, 0 },
221 Package(){0x0000FFFF, 3, INTB, 0 },
224 Name(APS6, Package(){
225 /* For Device(PBR6) APIC mode*/
226 Package(){0x0000FFFF, 0, 0, 18 },
227 Package(){0x0000FFFF, 1, 0, 19 },
228 Package(){0x0000FFFF, 2, 0, 16 },
229 Package(){0x0000FFFF, 3, 0, 17 },
233 /* For Device(PBR7) PIC mode*/
234 Package(){0x0000FFFF, 0, INTD, 0 },
235 Package(){0x0000FFFF, 1, INTA, 0 },
236 Package(){0x0000FFFF, 2, INTB, 0 },
237 Package(){0x0000FFFF, 3, INTC, 0 },
240 Name(APS7, Package(){
241 /* For Device(PBR7) APIC mode*/
242 Package(){0x0000FFFF, 0, 0, 19 },
243 Package(){0x0000FFFF, 1, 0, 16 },
244 Package(){0x0000FFFF, 2, 0, 17 },
245 Package(){0x0000FFFF, 3, 0, 18 },
249 /* For Device(PE20) PIC mode*/
250 Package(){0x0000FFFF, 0, INTA, 0 },
251 Package(){0x0000FFFF, 1, INTB, 0 },
252 Package(){0x0000FFFF, 2, INTC, 0 },
253 Package(){0x0000FFFF, 3, INTD, 0 },
256 Name(APE0, Package(){
257 /* For Device(PE20) APIC mode*/
258 Package(){0x0000FFFF, 0, 0, 16 },
259 Package(){0x0000FFFF, 1, 0, 17 },
260 Package(){0x0000FFFF, 2, 0, 18 },
261 Package(){0x0000FFFF, 3, 0, 19 },
265 /* For Device(PE21) PIC mode*/
266 Package(){0x0000FFFF, 0, INTB, 0 },
267 Package(){0x0000FFFF, 1, INTC, 0 },
268 Package(){0x0000FFFF, 2, INTD, 0 },
269 Package(){0x0000FFFF, 3, INTA, 0 },
272 Name(APE1, Package(){
273 /* For Device(PE21) APIC mode*/
274 Package(){0x0000FFFF, 0, 0, 17 },
275 Package(){0x0000FFFF, 1, 0, 18 },
276 Package(){0x0000FFFF, 2, 0, 19 },
277 Package(){0x0000FFFF, 3, 0, 16 },
281 /* For Device(PE22) PIC mode*/
282 Package(){0x0000FFFF, 0, INTC, 0 },
283 Package(){0x0000FFFF, 1, INTD, 0 },
284 Package(){0x0000FFFF, 2, INTA, 0 },
285 Package(){0x0000FFFF, 3, INTB, 0 },
288 Name(APE2, Package(){
289 /* For Device(PE22) APIC mode*/
290 Package(){0x0000FFFF, 0, 0, 18 },
291 Package(){0x0000FFFF, 1, 0, 19 },
292 Package(){0x0000FFFF, 2, 0, 16 },
293 Package(){0x0000FFFF, 3, 0, 17 },
297 /* For Device(PE23) PIC mode*/
298 Package(){0x0000FFFF, 0, INTD, 0 },
299 Package(){0x0000FFFF, 1, INTA, 0 },
300 Package(){0x0000FFFF, 2, INTB, 0 },
301 Package(){0x0000FFFF, 3, INTC, 0 },
304 Name(APE3, Package(){
305 /* For Device(PE23) APIC mode*/
306 Package(){0x0000FFFF, 0, 0, 19 },
307 Package(){0x0000FFFF, 1, 0, 16 },
308 Package(){0x0000FFFF, 2, 0, 17 },
309 Package(){0x0000FFFF, 3, 0, 18 },