src/mainboard/amd/dbm690t/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 #define RC0 (6<<8)
  21 #define RC1 (7<<8)
  22
  23 #define SMBUS_HUB 0x71
  24
  25 #include <stdint.h>
  26 #include <string.h>
  27 #include <device/pci_def.h>
  28 #include <arch/io.h>
  29 #include <device/pnp_def.h>
  30 #include <arch/romcc_io.h>
  31 #include <cpu/x86/lapic.h>
  32 #include <pc80/mc146818rtc.h>
  33 #include <console/console.h>
  34
  35 #include <cpu/amd/model_fxx_rev.h>
  36 #include "northbridge/amd/amdk8/raminit.h"
  37 #include "cpu/amd/model_fxx/apic_timer.c"
  38 #include "lib/delay.c"
  39
  40 #include "cpu/x86/lapic/boot_cpu.c"
  41 #include "northbridge/amd/amdk8/reset_test.c"
  42 #include "superio/ite/it8712f/it8712f_early_serial.c"
  43 #include <spd.h>
  44
  45 #include <usbdebug.h>
  46
  47 #include "cpu/x86/mtrr/earlymtrr.c"
  48 #include "cpu/x86/bist.h"
  49
  50 #include "northbridge/amd/amdk8/setup_resource_map.c"
  51
  52 #include "southbridge/amd/rs690/rs690_early_setup.c"
  53 #include "southbridge/amd/sb600/sb600_early_setup.c"
  54 #include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */
  55
  56 /* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
  57 static void memreset(int controllers, const struct mem_controller *ctrl)
  58 {
  59 }
  60
  61 /* called in raminit_f.c */
  62 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  63 {
  64 }
  65
  66 /*called in raminit_f.c */
  67 static inline int spd_read_byte(u32 device, u32 address)
  68 {
  69         return smbus_read_byte(device, address);
  70 }
  71
  72 #include "northbridge/amd/amdk8/amdk8.h"
  73 #include "northbridge/amd/amdk8/incoherent_ht.c"
  74 #include "northbridge/amd/amdk8/raminit_f.c"
  75 #include "northbridge/amd/amdk8/coherent_ht.c"
  76 #include "lib/generic_sdram.c"
  77 #include "resourcemap.c"
  78
  79 #include "cpu/amd/dualcore/dualcore.c"
  80
  81
  82 #include "cpu/amd/car/post_cache_as_ram.c"
  83
  84 #include "cpu/amd/model_fxx/init_cpus.c"
  85
  86 #include "cpu/amd/model_fxx/fidvid.c"
  87
  88 #include "northbridge/amd/amdk8/early_ht.c"
  89
  90 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  91 {
  92         static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
  93         int needs_reset = 0;
  94         u32 bsp_apicid = 0;
  95         msr_t msr;
  96         struct cpuid_result cpuid1;
  97         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
  98
  99         if (!cpu_init_detectedx && boot_cpu()) {
 100                 /* Nothing special needs to be done to find bus 0 */
 101                 /* Allow the HT devices to be found */
 102                 enumerate_ht_chain();
 103
 104                 /* sb600_lpc_port80(); */
 105                 sb600_pci_port80();
 106         }
 107
 108         if (bist == 0) {
 109                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 110         }
 111
 112         enable_rs690_dev8();
 113         sb600_lpc_init();
 114
 115         /* it8712f_enable_serial does not use its 1st parameter. */
 116         it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
 117         uart_init();
 118
 119 #if CONFIG_USBDEBUG
 120         sb600_enable_usbdebug(0);
 121         early_usbdebug_init();
 122 #endif
 123
 124         console_init();
 125
 126         /* Halt if there was a built in self test failure */
 127         report_bist_failure(bist);
 128         printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid);
 129
 130         setup_dbm690t_resource_map();
 131
 132         setup_coherent_ht_domain();
 133
 134 #if CONFIG_LOGICAL_CPUS==1
 135         /* It is said that we should start core1 after all core0 launched */
 136         wait_all_core0_started();
 137         start_other_cores();
 138 #endif
 139         wait_all_aps_started(bsp_apicid);
 140
 141         ht_setup_chains_x(sysinfo);
 142
 143         /* run _early_setup before soft-reset. */
 144         rs690_early_setup();
 145         sb600_early_setup();
 146
 147         /* Check to see if processor is capable of changing FIDVID  */
 148         /* otherwise it will throw a GP# when reading FIDVID_STATUS */
 149         cpuid1 = cpuid(0x80000007);
 150         if( (cpuid1.edx & 0x6) == 0x6 ) {
 151
 152                 /* Read FIDVID_STATUS */
 153                 msr=rdmsr(0xc0010042);
 154                 printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 155
 156                 enable_fid_change();
 157                 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 158                 init_fidvid_bsp(bsp_apicid);
 159
 160                 /* show final fid and vid */
 161                 msr=rdmsr(0xc0010042);
 162                 printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 163
 164         } else {
 165                 printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
 166         }
 167
 168         needs_reset = optimize_link_coherent_ht();
 169         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 170         rs690_htinit();
 171         printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
 172
 173         if (needs_reset) {
 174                 print_info("ht reset -\n");
 175                 soft_reset();
 176         }
 177
 178         allow_all_aps_stop(bsp_apicid);
 179
 180         /* It's the time to set ctrl now; */
 181         printk(BIOS_DEBUG, "sysinfo->nodes: %2x  sysinfo->ctrl: %p  spd_addr: %p\n",
 182                      sysinfo->nodes, sysinfo->ctrl, spd_addr);
 183         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 184         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 185
 186         rs690_before_pci_init();
 187         sb600_before_pci_init();
 188
 189         post_cache_as_ram();
 190 }
 191