2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <console/console.h>
22 #include <arch/smp/mpspec.h>
23 #include <device/pci.h>
28 #include <cpu/amd/amdk8_sysconf.h>
31 extern u8 bus_rs690[8];
32 extern u8 bus_sb600[2];
34 extern unsigned long apicid_sb600;
36 extern unsigned long bus_type[256];
37 extern unsigned long sbdn_rs690;
38 extern unsigned long sbdn_sb600;
40 extern void get_bus_conf(void);
42 void *smp_write_config_table(void *v)
44 static const char sig[4] = "PCMP";
45 static const char oem[8] = "ATI ";
46 static const char productid[12] = "DBM690T ";
47 struct mp_config_table *mc;
50 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
51 memset(mc, 0, sizeof(*mc));
53 memcpy(mc->mpc_signature, sig, sizeof(sig));
54 mc->mpc_length = sizeof(*mc); /* initially just the header */
56 mc->mpc_checksum = 0; /* not yet computed */
57 memcpy(mc->mpc_oem, oem, sizeof(oem));
58 memcpy(mc->mpc_productid, productid, sizeof(productid));
61 mc->mpc_entry_count = 0; /* No entries yet... */
62 mc->mpc_lapic = LAPIC_ADDR;
67 smp_write_processors(mc);
71 /* Bus: Bus ID Type */
72 /* define bus and isa numbers */
73 for (j = 0; j < bus_isa; j++) {
74 smp_write_bus(mc, j, (char *)"PCI ");
76 smp_write_bus(mc, bus_isa, (char *)"ISA ");
78 /* I/O APICs: APIC ID Version State Address */
85 dev_find_slot(bus_sb600[0],
86 PCI_DEVFN(sbdn_sb600 + 0x14, 0));
88 dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
89 smp_write_ioapic(mc, apicid_sb600, 0x11, dword);
91 /* Initialize interrupt mapping */
93 byte = pci_read_config8(dev, 0x63);
95 byte |= 0; /* 0: INTA, ...., 7: INTH */
96 pci_write_config8(dev, 0x63, byte);
99 dword = pci_read_config32(dev, 0xac);
101 dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
102 /* dword |= 1<<22; PIC and APIC co exists */
103 pci_write_config32(dev, 0xac, dword);
106 * 00:12.0: PROG SATA : INT F
107 * 00:13.0: INTA USB_0
108 * 00:13.1: INTB USB_1
109 * 00:13.2: INTC USB_2
110 * 00:13.3: INTD USB_3
111 * 00:13.4: INTC USB_4
114 * 00:14.2: Prog HDA : INT E
121 /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
122 smp_write_intsrc(mc, mp_ExtINT,
123 MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa,
124 0x0, apicid_sb600, 0x0);
125 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
126 bus_isa, 0x1, apicid_sb600, 0x1);
127 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
128 bus_isa, 0x0, apicid_sb600, 0x2);
129 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
130 bus_isa, 0x3, apicid_sb600, 0x3);
131 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
132 bus_isa, 0x4, apicid_sb600, 0x4);
133 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
134 bus_isa, 0x6, apicid_sb600, 0x6);
135 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
136 bus_isa, 0x7, apicid_sb600, 0x7);
137 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
138 bus_isa, 0xc, apicid_sb600, 0xc);
139 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
140 bus_isa, 0xd, apicid_sb600, 0xd);
141 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
142 bus_isa, 0xe, apicid_sb600, 0xe);
145 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
146 0, 19 << 2 | 0, apicid_sb600, 0x10);
147 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
148 0, 19 << 2 | 1, apicid_sb600, 0x11);
149 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
150 0, 19 << 2 | 2, apicid_sb600, 0x12);
151 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
152 0, 19 << 2 | 3, apicid_sb600, 0x13);
155 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
156 0, 18 << 2 | 0, apicid_sb600, 22);
158 /* HD Audio: b0:d20:f1:reg63 should be 0. */
159 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
160 0, 20 << 2 | 0, apicid_sb600, 16);
162 /* on board NIC & Slot PCIE. */
164 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
165 bus_rs690[1], 0x5 << 2 | 0, apicid_sb600, 18);
166 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
167 bus_rs690[1], 0x5 << 2 | 1, apicid_sb600, 19);
168 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
169 bus_rs690[2], 0x0 << 2 | 0, apicid_sb600, 18);
170 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
171 bus_rs690[3], 0x0 << 2 | 0, apicid_sb600, 19);
172 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
173 bus_rs690[4], 0x0 << 2 | 0, apicid_sb600, 16);
174 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
175 bus_rs690[5], 0x0 << 2 | 0, apicid_sb600, 17);
176 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
177 bus_rs690[6], 0x0 << 2 | 0, apicid_sb600, 18);
178 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
179 bus_rs690[7], 0x0 << 2 | 0, apicid_sb600, 19);
185 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
186 bus_sb600[1], 5 << 2 | 0, apicid_sb600, 20);
187 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
188 bus_sb600[1], 5 << 2 | 1, apicid_sb600, 21);
189 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
190 bus_sb600[1], 5 << 2 | 2, apicid_sb600, 22);
191 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
192 bus_sb600[1], 5 << 2 | 3, apicid_sb600, 23);
195 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
196 bus_sb600[1], 6 << 2 | 0, apicid_sb600, 21);
197 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
198 bus_sb600[1], 6 << 2 | 1, apicid_sb600, 22);
199 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
200 bus_sb600[1], 6 << 2 | 2, apicid_sb600, 23);
201 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
202 bus_sb600[1], 6 << 2 | 3, apicid_sb600, 20);
205 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
206 bus_sb600[1], 7 << 2 | 0, apicid_sb600, 22);
207 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
208 bus_sb600[1], 7 << 2 | 1, apicid_sb600, 23);
209 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
210 bus_sb600[1], 7 << 2 | 2, apicid_sb600, 20);
211 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
212 bus_sb600[1], 7 << 2 | 3, apicid_sb600, 21);
214 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
215 smp_write_intsrc(mc, mp_ExtINT,
216 MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa,
217 0x0, MP_APIC_ALL, 0x0);
218 smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
219 bus_isa, 0x0, MP_APIC_ALL, 0x1);
220 /* There is no extension information... */
222 /* Compute the checksums */
224 smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
225 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
226 printk_debug("Wrote the mp table end at: %p - %p\n",
227 mc, smp_next_mpe_entry(mc));
228 return smp_next_mpe_entry(mc);
231 unsigned long write_smp_table(unsigned long addr)
234 v = smp_write_floating_table(addr);
235 return (unsigned long)smp_write_config_table(v);