2 * This file is part of the LinuxBIOS project.
4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 #include <device/pci_def.h>
26 #include <device/pnp_def.h>
28 #include "pc80/serial.c"
29 #include "arch/i386/lib/console.c"
30 #include "ram/ramtest.c"
31 #include "cpu/x86/bist.h"
32 #include "cpu/x86/msr.h"
33 #include <cpu/amd/lxdef.h>
34 #include <cpu/amd/geode_post_code.h>
35 #include "southbridge/amd/cs5536/cs5536.h"
37 #define POST_CODE(x) outb(x, 0x80)
38 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
40 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"
41 #include "southbridge/amd/cs5536/cs5536_early_setup.c"
42 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
44 static inline int spd_read_byte(unsigned int device, unsigned int address)
46 return smbus_read_byte(device, address);
49 #define ManualConf 0 /* Do automatic strapped PLL config */
50 #define PLLMSRhi 0x00001490 /* Manual settings for the PLL */
51 #define PLLMSRlo 0x02000030
55 #include "northbridge/amd/lx/raminit.h"
56 #include "northbridge/amd/lx/pll_reset.c"
57 #include "northbridge/amd/lx/raminit.c"
58 #include "sdram/generic_sdram.c"
59 #include "cpu/amd/model_lx/cpureginit.c"
60 #include "cpu/amd/model_lx/syspreinit.c"
62 static void msr_init(void)
66 /* Setup access to the cache for under 1MB. */
68 msr.lo = 0x1000A000; /* 0-A0000 write back */
69 wrmsr(CPU_RCONF_DEFAULT, msr);
71 msr.hi = 0x0; /* Write back */
73 wrmsr(CPU_RCONF_A0_BF, msr);
74 wrmsr(CPU_RCONF_C0_DF, msr);
75 wrmsr(CPU_RCONF_E0_FF, msr);
77 /* Setup access to the cache for under 640K. Note MC not setup yet. */
80 wrmsr(MSR_GLIU0 + 0x20, msr);
84 wrmsr(MSR_GLIU0 + 0x21, msr);
88 wrmsr(MSR_GLIU1 + 0x20, msr);
92 wrmsr(MSR_GLIU1 + 0x21, msr);
95 static void mb_gpio_init(void)
97 /* Early mainboard specific GPIO setup. */
100 void cache_as_ram_main(void)
104 static const struct mem_controller memctrl[] = {
105 {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
111 cs5536_early_setup();
113 /* Note: must do this AFTER the early_setup! It is counting on some
114 * early MSR setup for CS5536.
116 w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
121 pll_reset(ManualConf);
125 sdram_initialize(1, memctrl);
128 /* ram_check(0x00000000, 640 * 1024); */
130 /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */