src/mainboard/amd/db800/Config.lb

   1 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
   2 default CONFIG_XIP_ROM_SIZE = 64 * 1024
   3 include /config/nofailovercalculation.lb
   4
   5 ##
   6 ## Set all of the defaults for an x86 architecture
   7 ##
   8
   9 arch i386 end
  10
  11 ##
  12 ## Build the objects we have code for in this directory.
  13 ##
  14
  15 driver mainboard.o
  16
  17 if CONFIG_GENERATE_PIRQ_TABLE
  18         object irq_tables.o
  19 end
  20
  21         #compile cache_as_ram.c to auto.inc
  22         makerule ./cache_as_ram_auto.inc
  23                         depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
  24                         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
  25                         action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
  26                         action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
  27         end
  28
  29 ##
  30 ## Build our 16 bit and 32 bit coreboot entry code
  31 ##
  32 mainboardinit cpu/x86/16bit/entry16.inc
  33 mainboardinit cpu/x86/32bit/entry32.inc
  34 ldscript /cpu/x86/16bit/entry16.lds
  35 ldscript /cpu/x86/32bit/entry32.lds
  36
  37 ##
  38 ## Build our reset vector (This is where coreboot is entered)
  39 ##
  40 if CONFIG_USE_FALLBACK_IMAGE
  41         mainboardinit cpu/x86/16bit/reset16.inc
  42         ldscript /cpu/x86/16bit/reset16.lds
  43 else
  44         mainboardinit cpu/x86/32bit/reset32.inc
  45         ldscript /cpu/x86/32bit/reset32.lds
  46 end
  47
  48 ### Should this be in the northbridge code?
  49 #not in serengeti_cheetah mainboardinit arch/i386/lib/cpu_reset.inc
  50
  51 ##
  52 ## Include an id string (For safe flashing)
  53 ##
  54 mainboardinit arch/i386/lib/id.inc
  55 ldscript /arch/i386/lib/id.lds
  56
  57 ###
  58 ### This is the early phase of coreboot startup
  59 ### Things are delicate and we test to see if we should
  60 ### failover to another image.
  61 ###
  62 if CONFIG_USE_FALLBACK_IMAGE
  63         ldscript /arch/i386/lib/failover.lds
  64 #       mainboardinit ./failover.inc
  65 end
  66
  67 ###
  68 ### O.k. We aren't just an intermediary anymore!
  69 ###
  70
  71 ##
  72 ## Setup RAM
  73 ##
  74 mainboardinit cpu/x86/fpu_enable.inc
  75
  76         mainboardinit cpu/amd/model_lx/cache_as_ram.inc
  77         mainboardinit ./cache_as_ram_auto.inc
  78
  79 ##
  80 ## Include the secondary Configuration files
  81 ##
  82 dir /pc80
  83 config chip.h
  84
  85 chip northbridge/amd/lx
  86         device pci_domain 0 on
  87                 device pci 1.0 on end                           # Northbridge
  88                 device pci 1.1 on end                           # Graphics
  89                 chip southbridge/amd/cs5536
  90                         # IRQ 12 and 1 unmasked,  Keyboard and Mouse IRQs. OK
  91                         # SIRQ Mode = Active(Quiet) mode. Save power....
  92                         # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK
  93                         register "lpc_serirq_enable" = "0x0000105a"
  94                         register "lpc_serirq_polarity" = "0x0000EFA5"
  95                         register "lpc_serirq_mode" = "1"
  96                         register "enable_gpio_int_route" = "0x0D0C0700"
  97                         register "enable_ide_nand_flash" = "0"  # 0:ide mode, 1:flash
  98                         register "enable_USBP4_device" = "1"    # 0: host, 1:device
  99                         register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
 100                         register "com1_enable" = "0"
 101                         register "com1_address" = "0x3F8"
 102                         register "com1_irq" = "4"
 103                         register "com2_enable" = "0"
 104                         register "com2_address" = "0x2F8"
 105                         register "com2_irq" = "3"
 106                         register "unwanted_vpci[0]" = "0"       # End of list has a zero
 107                         device pci d.0 on end                   # Ethernet
 108                         device pci e.0 on end                   # Slot1
 109                         device pci f.0 on                       # ISA Bridge
 110                                 chip superio/winbond/w83627hf
 111                                         device pnp 2e.0 off     # Floppy
 112                                                 io 0x60 = 0x3f0
 113                                                 irq 0x70 = 6
 114                                                 drq 0x74 = 2
 115                                         end
 116                                         device pnp 2e.1 off     # Parallel port
 117                                                 io 0x60 = 0x378
 118                                                 irq 0x70 = 7
 119                                         end
 120                                         device pnp 2e.2 on      # Com1
 121                                                 io 0x60 = 0x3f8
 122                                                 irq 0x70 = 4
 123                                         end
 124                                         device pnp 2e.3 off end # Com2
 125                                         device pnp 2e.5 on      # Keyboard
 126                                                 io 0x60 = 0x60
 127                                                 io 0x62 = 0x64
 128                                                 irq 0x70 = 1
 129                                                 irq 0x72 = 12
 130                                         end
 131                                         device pnp 2e.6 off end # CIR
 132                                         device pnp 2e.7 off end # GAME_MIDI_GIPO1
 133                                         device pnp 2e.8 off end # GPIO2
 134                                         device pnp 2e.9 off end # GPIO3
 135                                         device pnp 2e.a off end # ACPI
 136                                         device pnp 2e.b off end # HW Monitor
 137                                 end
 138                         end
 139                         device pci f.2 on end                   # IDE Controller
 140                         device pci f.3 on end                   # Audio
 141                         device pci f.4 on end                   # OHCI
 142                         device pci f.5 on end                   # EHCI
 143                 end
 144         end
 145         # APIC cluster is late CPU init.
 146         device apic_cluster 0 on
 147                 chip cpu/amd/model_lx
 148                         device apic 0 on end
 149                 end
 150         end
 151 end
 152