src/mainboard/amd/bimini_fam10/mptable.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2010 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 #include <console/console.h>
  21 #include <arch/smp/mpspec.h>
  22 #include <device/pci.h>
  23 #include <arch/io.h>
  24 #include <string.h>
  25 #include <stdint.h>
  26 #include "pmio.h"
  27 #include <cpu/amd/amdfam10_sysconf.h>
  28
  29 extern int bus_isa;
  30 extern u8 bus_rs780[11];
  31 extern u8 bus_sb800[2];
  32 extern u32 apicid_sb800;
  33 extern u32 bus_type[256];
  34 extern u32 sbdn_rs780;
  35 extern u32 sbdn_sb800;
  36
  37 u8 intr_data[] = {
  38         [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
  39         [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
  40         [0x10] = 0x1F,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
  41         0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
  42         0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
  43         0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
  44         0x10,0x11,0x12,0x13
  45 };
  46
  47 static void *smp_write_config_table(void *v)
  48 {
  49         static const char sig[4] = "PCMP";
  50         static const char oem[8] = "COREBOOT";
  51         static const char productid[12] = "BIMINI      ";
  52         struct mp_config_table *mc;
  53         u32 dword;
  54         u8 byte;
  55
  56         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
  57         memset(mc, 0, sizeof(*mc));
  58
  59         memcpy(mc->mpc_signature, sig, sizeof(sig));
  60         mc->mpc_length = sizeof(*mc);   /* initially just the header */
  61         mc->mpc_spec = 0x04;
  62         mc->mpc_checksum = 0;   /* not yet computed */
  63         memcpy(mc->mpc_oem, oem, sizeof(oem));
  64         memcpy(mc->mpc_productid, productid, sizeof(productid));
  65         mc->mpc_oemptr = 0;
  66         mc->mpc_oemsize = 0;
  67         mc->mpc_entry_count = 0;        /* No entries yet... */
  68         mc->mpc_lapic = LAPIC_ADDR;
  69         mc->mpe_length = 0;
  70         mc->mpe_checksum = 0;
  71         mc->reserved = 0;
  72
  73         smp_write_processors(mc);
  74
  75         get_bus_conf();
  76
  77         mptable_write_buses(mc, NULL, &bus_isa);
  78
  79         /* I/O APICs:   APIC ID Version State   Address */
  80
  81         dword = 0;
  82         dword = pm_ioread(0x34) & 0xF0;
  83         dword |= (pm_ioread(0x35) & 0xFF) << 8;
  84         dword |= (pm_ioread(0x36) & 0xFF) << 16;
  85         dword |= (pm_ioread(0x37) & 0xFF) << 24;
  86         smp_write_ioapic(mc, apicid_sb800, 0x11, dword);
  87
  88         for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
  89                 outb(byte | 0x80, 0xC00);
  90                 outb(intr_data[byte], 0xC01);
  91         }
  92
  93         /* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
  94 #define IO_LOCAL_INT(type, intr, apicid, pin) \
  95         smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
  96
  97         mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
  98
  99         /* PCI interrupts are level triggered, and are
 100          * associated with a specific bus/device/function tuple.
 101          */
 102 #if CONFIG_GENERATE_ACPI_TABLES == 0
 103 #define PCI_INT(bus, dev, fn, pin) \
 104         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
 105 #else
 106 #define PCI_INT(bus, dev, fn, pin)
 107 #endif
 108
 109         PCI_INT(0x0, 0x14, 0x0, 0x10);
 110         /* HD Audio: */
 111         PCI_INT(0x0, 0x14, 0x2, 0x12);
 112
 113         PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
 114         PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
 115         PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
 116         PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
 117         PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
 118         PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
 119
 120         /* sata */
 121         PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
 122
 123         /* on board NIC & Slot PCIE.  */
 124         /* PCI_INT(bus_rs780[0x1], 0x5, 0x0, 0x12); */
 125 /*      PCI_INT(bus_rs780[0x1], 0x5, 0x1, 0x13); */
 126         PCI_INT(bus_rs780[0x2], 0x0, 0x0, 0x12); /* Dev 2, external GFX */
 127         /* PCI_INT(bus_rs780[0x3], 0x0, 0x0, 0x13); */
 128         PCI_INT(bus_rs780[0x4], 0x0, 0x0, 0x10);
 129         /* configuration B doesnt need dev 5,6,7 */
 130         /*
 131          * PCI_INT(bus_rs780[0x5], 0x0, 0x0, 0x11);
 132          * PCI_INT(bus_rs780[0x6], 0x0, 0x0, 0x12);
 133          * PCI_INT(bus_rs780[0x7], 0x0, 0x0, 0x13);
 134          */
 135         PCI_INT(bus_rs780[0x9], 0x0, 0x0, 0x11);
 136         PCI_INT(bus_rs780[0xA], 0x0, 0x0, 0x12); /* NIC */
 137
 138         /* PCI slots */
 139         /* PCI_SLOT 0. */
 140         PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
 141         PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
 142         PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
 143         PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
 144
 145         /* PCI_SLOT 1. */
 146         PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
 147         PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
 148         PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
 149         PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
 150
 151         /* PCI_SLOT 2. */
 152         PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
 153         PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
 154         PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
 155         PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
 156
 157         /*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
 158         IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
 159         IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
 160         /* There is no extension information... */
 161
 162         /* Compute the checksums */
 163         mc->mpe_checksum =
 164             smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 165         mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
 166         printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 167                      mc, smp_next_mpe_entry(mc));
 168         return smp_next_mpe_entry(mc);
 169 }
 170
 171 unsigned long write_smp_table(unsigned long addr)
 172 {
 173         void *v;
 174         v = smp_write_floating_table(addr);
 175         return (unsigned long)smp_write_config_table(v);
 176 }