src/mainboard/agami/aruma/Config.lb

   1 ##
   2 ## Compute the location and size of where this firmware image
   3 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
   4 ##
   5 if USE_FALLBACK_IMAGE
   6         default ROM_SECTION_SIZE   = FALLBACK_SIZE
   7         default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
   8 else
   9         default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
  10         default ROM_SECTION_OFFSET = 0
  11 end
  12
  13 ##
  14 ## Compute the start location and size size of
  15 ## The linuxBIOS bootloader.
  16 ##
  17 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
  18 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
  19
  20 ##
  21 ## Compute where this copy of linuxBIOS will start in the boot rom
  22 ##
  23 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
  24
  25 ##
  26 ## Compute a range of ROM that can cached to speed up linuxBIOS,
  27 ## execution speed.
  28 ##
  29 ## XIP_ROM_SIZE must be a power of 2.
  30 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
  31 ##
  32 default XIP_ROM_SIZE=65536
  33 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
  34
  35 arch i386 end
  36
  37 ##
  38 ## Build the objects we have code for in this directory.
  39 ##
  40
  41 driver mainboard.o
  42 if HAVE_MP_TABLE object mptable.o end
  43 if HAVE_PIRQ_TABLE object irq_tables.o end
  44
  45 #needed by irq_tables and mptable and acpi_tables
  46 object get_bus_conf.o
  47
  48 if HAVE_ACPI_TABLES
  49         object acpi_tables.o
  50         object fadt.o
  51
  52         makerule dsdt.c
  53                 depends "$(MAINBOARD)/dx/dsdt_lb.dsl"
  54                 action  "iasl -tc $(MAINBOARD)/dx/dsdt_lb.dsl"
  55                 action  "mv dsdt_lb.hex dsdt.c"
  56         end
  57         object ./dsdt.o
  58
  59         makerule ssdt.c
  60                 depends "$(MAINBOARD)/ssdt_lb_x.dsl"
  61                 action  "iasl -tc $(MAINBOARD)/ssdt_lb_x.dsl"
  62                 action  "perl -pi -e 's/AmlCode/AmlCode_ssdt/g' ssdt_lb_x.hex"
  63                 action  "mv ssdt_lb_x.hex ssdt.c"
  64         end
  65         object ./ssdt.o
  66
  67         if ACPI_SSDTX_NUM
  68                 makerule ssdt2.c
  69                         depends "$(MAINBOARD)/dx/pci2.asl"
  70                         action  "iasl -tc $(MAINBOARD)/dx/pci2.asl"
  71                         action  "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex"
  72                         action  "mv pci2.hex ssdt2.c"
  73                 end
  74                 object ./ssdt2.o
  75                 makerule ssdt3.c
  76                         depends "$(MAINBOARD)/dx/pci3.asl"
  77                         action  "iasl -tc $(MAINBOARD)/dx/pci3.asl"
  78                         action  "perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex"
  79                         action  "mv pci3.hex ssdt3.c"
  80                 end
  81                 object ./ssdt3.o
  82                 makerule ssdt4.c
  83                         depends "$(MAINBOARD)/dx/pci4.asl"
  84                         action  "iasl -tc $(MAINBOARD)/dx/pci4.asl"
  85                         action  "perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex"
  86                         action  "mv pci4.hex ssdt4.c"
  87                 end
  88                 object ./ssdt4.o
  89
  90         end
  91 end
  92
  93
  94
  95 #object reset.o
  96
  97
  98 if USE_DCACHE_RAM
  99
 100         if CONFIG_USE_INIT
 101                 # compile cache_as_ram.c to auto.o
 102                 makerule ./cache_as_ram_auto.o
 103                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
 104                         action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o cache_as_ram_auto.o"
 105                 end
 106
 107         else
 108                 #compile cache_as_ram.c to auto.inc
 109                 makerule ./cache_as_ram_auto.inc
 110                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
 111                         action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
 112                         action "perl -e 's/.rodata/.rom.data/g' -pi $@"
 113                         action "perl -e 's/.text/.section .rom.text/g' -pi $@"
 114                 end
 115
 116         end
 117 else
 118
 119         ##
 120         ## Romcc output
 121         ##
 122         makerule ./failover.E
 123                 depends "$(MAINBOARD)/failover.c ./romcc"
 124                 action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 125         end
 126
 127         makerule ./failover.inc
 128                 depends "$(MAINBOARD)/failover.c ./romcc"
 129                 action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 130         end
 131
 132         makerule ./auto.E
 133                 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
 134                 action  "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 135         end
 136         makerule ./auto.inc
 137                 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
 138                 action  "./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 139         end
 140
 141 end
 142 ##
 143 ## Build our 16 bit and 32 bit linuxBIOS entry code
 144 ##
 145
 146 mainboardinit cpu/x86/16bit/entry16.inc
 147 ldscript /cpu/x86/16bit/entry16.lds
 148
 149 mainboardinit cpu/x86/32bit/entry32.inc
 150 if USE_DCACHE_RAM
 151         if CONFIG_USE_INIT
 152                 ldscript /cpu/x86/32bit/entry32.lds
 153         end
 154
 155         if CONFIG_USE_INIT
 156                 ldscript /cpu/amd/car/cache_as_ram.lds
 157         end
 158 end
 159
 160 ##
 161 ## Build our reset vector (This is where linuxBIOS is entered)
 162 ##
 163 if USE_FALLBACK_IMAGE
 164         mainboardinit cpu/x86/16bit/reset16.inc
 165         ldscript /cpu/x86/16bit/reset16.lds
 166 else
 167         mainboardinit cpu/x86/32bit/reset32.inc
 168         ldscript /cpu/x86/32bit/reset32.lds
 169 end
 170
 171 if USE_DCACHE_RAM
 172 else
 173         ### Should this be in the northbridge code?
 174         mainboardinit arch/i386/lib/cpu_reset.inc
 175 end
 176
 177 ##
 178 ## Include an id string (For safe flashing)
 179 ##
 180 mainboardinit arch/i386/lib/id.inc
 181 ldscript /arch/i386/lib/id.lds
 182
 183 if USE_DCACHE_RAM
 184         ##
 185         ## Setup Cache-As-Ram
 186         ##
 187         mainboardinit cpu/amd/car/cache_as_ram.inc
 188 end
 189
 190 ###
 191 ### This is the early phase of linuxBIOS startup
 192 ### Things are delicate and we test to see if we should
 193 ### failover to another image.
 194 ###
 195 if USE_FALLBACK_IMAGE
 196         if USE_DCACHE_RAM
 197                 ldscript /arch/i386/lib/failover.lds
 198         else
 199                 ldscript /arch/i386/lib/failover.lds
 200                 mainboardinit ./failover.inc
 201         end
 202 end
 203
 204 ###
 205 ### O.k. We aren't just an intermediary anymore!
 206 ###
 207
 208 ##
 209 ## Setup RAM
 210 ##
 211 if USE_DCACHE_RAM
 212
 213         if CONFIG_USE_INIT
 214                 initobject cache_as_ram_auto.o
 215         else
 216                 mainboardinit ./cache_as_ram_auto.inc
 217         end
 218
 219 else
 220
 221         ##
 222         ## Setup RAM
 223         ##
 224         mainboardinit cpu/x86/fpu/enable_fpu.inc
 225         mainboardinit cpu/x86/mmx/enable_mmx.inc
 226         mainboardinit cpu/x86/sse/enable_sse.inc
 227         mainboardinit ./auto.inc
 228         mainboardinit cpu/x86/sse/disable_sse.inc
 229         mainboardinit cpu/x86/mmx/disable_mmx.inc
 230
 231 end
 232
 233 ##
 234 ## Include the secondary Configuration files
 235 ##
 236
 237 dir /pc80
 238
 239 if CONFIG_CHIP_NAME
 240         config chip.h
 241 end
 242
 243 # config for agami/aruma
 244 chip northbridge/amd/amdk8/root_complex
 245         device apic_cluster 0 on
 246                 chip cpu/amd/socket_940
 247                         device apic 0 on end
 248                 end
 249         end
 250         device pci_domain 0 on
 251             chip northbridge/amd/amdk8
 252                 device pci 18.0 on end #  device pci 18.0
 253                 device pci 18.0 on
 254                         #  devices on link 1, link 1 == LDT 1
 255                         chip southbridge/amd/amd8131
 256                                 # the on/off keyword is mandatory
 257                                 device pci 0.0 on end
 258                                 device pci 0.1 on end
 259                                 device pci 1.0 on end
 260                                 device pci 1.1 on end
 261                         end # 8131
 262                         chip southbridge/amd/amd8111
 263                                 # this "device pci 0.0" is the parent the next one
 264                                 # PCI bridge
 265                                 device pci 0.0 on
 266                                         device pci 0.0 on end
 267                                         device pci 0.1 on end
 268                                         device pci 0.2 off end
 269                                         device pci 1.0 off end
 270                                         #chip drivers/ati/ragexl
 271                                         chip drivers/pci/onboard
 272                                                 device pci 4.0 on end
 273                                                 register "rom_address" = "0xfff80000"
 274                                         end
 275                                 end
 276                                 device pci 1.0 on
 277                                         chip superio/winbond/w83627hf
 278                                                device pnp 2e.0 on #  Floppy
 279                                                         io 0x60 = 0x3f0
 280                                                         irq 0x70 = 6
 281                                                         drq 0x74 = 2
 282                                                 end
 283                                                 device pnp 2e.1 off #  Parallel Port
 284                                                         io 0x60 = 0x378
 285                                                         irq 0x70 = 7
 286                                                 end
 287                                                 device pnp 2e.2 on #  Com1
 288                                                         io 0x60 = 0x3f8
 289                                                         irq 0x70 = 4
 290                                                 end
 291                                                 device pnp 2e.3 on #  Com2
 292                                                         io 0x60 = 0x2f8
 293                                                         irq 0x70 = 3
 294                                                 end
 295                                                 device pnp 2e.5 on #  Keyboard
 296                                                         io 0x60 = 0x60
 297                                                         io 0x62 = 0x64
 298                                                         irq 0x70 = 1
 299                                                         irq 0x72 = 12
 300                                                 end
 301                                                 device pnp 2e.6 off #  CIR
 302                                                         io 0x60 = 0x100
 303                                                 end
 304                                                 device pnp 2e.7 off # GAME_MIDI_GIPO1
 305                                                         io 0x60 = 0x201
 306                                                         io 0x62 = 0x330
 307                                                         irq 0x70 = 9
 308                                                 end
 309                                                 device pnp 2e.8 off end # GPIO2
 310                                                 device pnp 2e.9 off end # GPIO3
 311                                                 device pnp 2e.a off end #  ACPI
 312                                                 device pnp 2e.b on #  HW Monitor
 313                                                         io 0x60 = 0x290
 314                                                         irq 0x70 = 5
 315                                                 end
 316                                         end
 317                                 end
 318                                 device pci 1.1 on end
 319                                 device pci 1.2 on end
 320                                 device pci 1.3 on
 321                                         chip drivers/generic/generic
 322                                                 #phillips pca9545 smbus mux
 323                                                 device i2c 70 on
 324                                                         # analog_devices adm1026
 325                                                         chip drivers/generic/generic
 326                                                                 device i2c 2c on end
 327                                                         end
 328                                                 end
 329                                                 device i2c 70 on end
 330                                                 device i2c 70 on end
 331                                                 device i2c 70 on end
 332                                         end
 333 #                                       chip drivers/generic/generic #dimm 0-0-0
 334 #                                               device i2c 50 on end
 335 #                                       end
 336 #                                       chip drivers/generic/generic #dimm 0-0-1
 337 #                                               device i2c 51 on end
 338 #                                       end
 339 #                                       chip drivers/generic/generic #dimm 0-1-0
 340 #                                               device i2c 52 on end
 341 #                                       end
 342 #                                       chip drivers/generic/generic #dimm 0-1-1
 343 #                                               device i2c 53 on end
 344 #                                       end
 345 #                                       chip drivers/generic/generic #dimm 1-0-0
 346 #                                               device i2c 54 on end
 347 #                                       end
 348 #                                       chip drivers/generic/generic #dimm 1-0-1
 349 #                                               device i2c 55 on end
 350 #                                       end
 351 #                                       chip drivers/generic/generic #dimm 1-1-0
 352 #                                               device i2c 56 on end
 353 #                                       end
 354 #                                       chip drivers/generic/generic #dimm 1-1-1
 355 #                                               device i2c 57 on end
 356 #                                       end
 357                                 end
 358                                 device pci 1.5 off end
 359                                 device pci 1.6 on end
 360                                 register "ide0_enable" = "1"
 361                                 register "ide1_enable" = "1"
 362                         end # 8111
 363                 end # LDT1
 364                 device pci 18.0 on end # LDT2
 365                 device pci 18.1 on end
 366                 device pci 18.2 on end
 367                 device pci 18.3 on end
 368             end
 369
 370                 chip northbridge/amd/amdk8
 371                         device pci 19.0 on end # LDT0
 372                         device pci 19.0 on end # LDT1
 373                         device pci 19.0 on # LDT2
 374                                 chip southbridge/amd/amd8131
 375                                         # the on/off keyword is mandatory
 376                                         device pci 0.0 on end
 377                                         device pci 0.1 on end
 378                                         device pci 1.0 on end
 379                                         device pci 1.1 on end
 380                                 end
 381                                 chip southbridge/amd/amd8131
 382                                         # the on/off keyword is mandatory
 383                                         device pci 0.0 on end
 384                                         device pci 0.1 on end
 385                                         device pci 1.0 on end
 386                                         device pci 1.1 on end
 387                                 end
 388                         end # LDT2
 389                         device pci 19.1 on end
 390                         device pci 19.2 on end
 391                         device pci 19.3 on end
 392                 end
 393
 394                 chip northbridge/amd/amdk8
 395                         device pci 1a.0 on end
 396                         device pci 1a.0 on end
 397                         device pci 1a.0 on # LDT2
 398                                 chip southbridge/amd/amd8131
 399                                         # the on/off keyword is mandatory
 400                                         device pci 0.0 on end
 401                                         device pci 0.1 on end
 402                                         device pci 1.0 on end
 403                                         device pci 1.1 on end
 404                                 end
 405                                 chip southbridge/amd/amd8131
 406                                         # the on/off keyword is mandatory
 407                                         device pci 0.0 on end
 408                                         device pci 0.1 on end
 409                                         device pci 1.0 on end
 410                                         device pci 1.1 on end
 411                                 end
 412
 413                         end # LDT2
 414                         device pci 1a.1 on end
 415                         device pci 1a.2 on end
 416                         device pci 1a.3 on end
 417                 end
 418
 419                 chip northbridge/amd/amdk8
 420                         device pci 1b.0 on end
 421                         device pci 1b.0 on # LDT1
 422                                 chip southbridge/amd/amd8131
 423                                         # the on/off keyword is mandatory
 424                                         device pci 0.0 on end
 425                                         device pci 0.1 on end
 426                                         device pci 1.0 on end
 427                                         device pci 1.1 on end
 428                                 end
 429                                 chip southbridge/amd/amd8131
 430                                         # the on/off keyword is mandatory
 431                                         device pci 0.0 on end
 432                                         device pci 0.1 on end
 433                                         device pci 1.0 on end
 434                                         device pci 1.1 on end
 435                                 end
 436
 437                         end
 438                         device pci 1b.0 on end
 439                         device pci 1b.1 on end
 440                         device pci 1b.2 on end
 441                         device pci 1b.3 on end
 442                 end
 443
 444
 445         end
 446 end
 447