src/mainboard/advantech/som_gx533c/auto.c

   1 #define ASSEMBLY 1
   2
   3 #include <stdint.h>
   4 #include <device/pci_def.h>
   5 #include <arch/io.h>
   6 #include <device/pnp_def.h>
   7 #include <arch/romcc_io.h>
   8 #include <arch/hlt.h>
   9 #include "pc80/serial.c"
  10 #include "arch/i386/lib/console.c"
  11 #include "ram/ramtest.c"
  12 #include "superio/nsc/pc87360/pc87360_early_serial.c"
  13 #include "cpu/x86/bist.h"
  14 #include "cpu/x86/msr.h"
  15 #include <cpu/amd/gx2def.h>
  16
  17 #define SERIAL_DEV PNP_DEV(0x2e,  PC87360_SP1)
  18
  19 #include "southbridge/amd/cs5535/cs5535_early_smbus.c"
  20 #include "southbridge/amd/cs5535/cs5535_early_setup.c"
  21 #include "northbridge/amd/gx2/raminit.h"
  22
  23 /* this has to be done on a per-mainboard basis, esp. if you don't have smbus */
  24 static void sdram_set_spd_registers(const struct mem_controller *ctrl)
  25 {
  26         msr_t msr;
  27         /* 1. Initialize GLMC registers base on SPD values,
  28          * Hard coded as XpressROM for now */
  29         //print_debug("sdram_enable step 1\r\n");
  30         msr = rdmsr(0x20000018);
  31         msr.hi = 0x10075012;
  32         msr.lo = 0x3900;
  33         wrmsr(0x20000018, msr);
  34
  35         msr = rdmsr(0x20000019);
  36         msr.hi = 0x18000008;
  37         msr.lo = 0x696332a3;
  38         wrmsr(0x20000019, msr);
  39
  40 }
  41
  42 #include "northbridge/amd/gx2/raminit.c"
  43 #include "sdram/generic_sdram.c"
  44
  45 #define PLLMSRhi 0x00000226
  46 #define PLLMSRlo 0x00000008
  47 #define PLLMSRlo1 ((0xde << 16) | (1 << 26) | (1 << 24))
  48 #define PLLMSRlo2 ((1<<14) |(1<<13) | (1<<0))
  49 #include "northbridge/amd/gx2/pll_reset.c"
  50
  51
  52 static void msr_init(void)
  53 {
  54         __builtin_wrmsr(0x1808,  0x10f3bf00, 0x22fffc02);
  55
  56         __builtin_wrmsr(0x10000020, 0xfff80, 0x20000000);
  57         __builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000);
  58         __builtin_wrmsr(0x10000026, 0x400fffc0, 0x2cfbc040);
  59         __builtin_wrmsr(0x10000027, 0xfff00000, 0xff);
  60         __builtin_wrmsr(0x10000028, 0x7bf00100, 0x2000000f);
  61         __builtin_wrmsr(0x1000002c, 0xff030003, 0x20000000);
  62
  63         __builtin_wrmsr(0x10000080, 0x3, 0x0);
  64
  65         __builtin_wrmsr(0x40000020, 0xfff80, 0x20000000);
  66         __builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000);
  67         __builtin_wrmsr(0x40000023, 0x400fffc0, 0x20000040);
  68         __builtin_wrmsr(0x40000024, 0xff4ffffc, 0x200000ef);
  69         __builtin_wrmsr(0x40000029, 0x7bf00100, 0x2000000f);
  70         __builtin_wrmsr(0x4000002d, 0xff030003, 0x20000000);
  71
  72
  73         __builtin_wrmsr(0x50002001, 0x27, 0x0);
  74         __builtin_wrmsr(0x4c002001, 0x1, 0x0);
  75 }
  76
  77
  78 static void main(unsigned long bist)
  79 {
  80         static const struct mem_controller memctrl [] = {
  81                 {.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
  82         };
  83         unsigned char temp;
  84
  85         msr_init();
  86
  87         pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE);
  88         uart_init();
  89         console_init();
  90
  91         cs5535_early_setup();
  92         print_err("done cs5535 early\n");
  93         pll_reset();
  94         print_err("done pll_reset\n");
  95         /* Halt if there was a built in self test failure */
  96         //report_bist_failure(bist);
  97
  98         sdram_initialize(1, memctrl);
  99
 100         print_err("Done sdram_initialize\n");
 101         print_err("Disable watchdog\n");
 102         outb( 0x87, 0x4E);                            //enter SuperIO configuration mode
 103         outb( 0x87, 0x4E);
 104
 105
 106         outb(0x20, 0x4e);
 107         temp = inb(0x4f);
 108         print_debug_hex8(temp);
 109         if (temp != 0x52){
 110                 print_err("CAN NOT READ SUPERIO VID\n");
 111         }
 112
 113         outb(0x29, 0x4e);
 114         outb(0x7c, 0x4f);
 115
 116         outb( 0x07, 0x4E);                            //enable logical device 9
 117         outb( 0x09, 0x4F);
 118         outb(0x30, 0x4e);
 119         outb(1, 0x4f);
 120         outb( 0xF0, 0x4E);                            //set GP33 as outbut in configuration register F0h     Bit4 = \u20180\u2019
 121         outb( 0xC7, 0x4F);
 122         outb( 0xF1, 0x4E);                            //clr GP33 (Bit4) value in cofiguration register F1h to \u20181\u2019 disables
 123         temp = inb(0x4F);                            //watchdog function. Make sure to let the other Bits unchanged!
 124         print_debug_hex8(temp);print_debug(":");
 125         temp = temp & ~8;
 126         outb( temp, 0x4F);
 127         temp = inb(0x4F);                            //watchdog function. Make sure to let the other Bits unchanged!
 128         print_debug_hex8(temp);print_debug("\n");
 129         /* Check all of memory */
 130 //      ram_check(0, 16384);
 131 //      ram_check(0x20000, 0x24000);
 132 //      ram_check(0x00000000, 640*1024);
 133
 134 }