2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 ## XIP_ROM_SIZE must be a power of 2.
22 default XIP_ROM_SIZE = 64 * 1024
23 include /config/nofailovercalculation.lb
31 depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
32 action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
34 makerule ./failover.inc
35 depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
36 action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
39 # depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
40 depends "$(MAINBOARD)/auto.c ../romcc"
41 action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
44 # depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
45 depends "$(MAINBOARD)/auto.c ../romcc"
46 action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
48 mainboardinit cpu/x86/16bit/entry16.inc
49 mainboardinit cpu/x86/32bit/entry32.inc
50 ldscript /cpu/x86/16bit/entry16.lds
51 ldscript /cpu/x86/32bit/entry32.lds
53 mainboardinit cpu/x86/16bit/reset16.inc
54 ldscript /cpu/x86/16bit/reset16.lds
56 mainboardinit cpu/x86/32bit/reset32.inc
57 ldscript /cpu/x86/32bit/reset32.lds
59 mainboardinit arch/i386/lib/cpu_reset.inc
60 mainboardinit arch/i386/lib/id.inc
61 ldscript /arch/i386/lib/id.lds
63 ldscript /arch/i386/lib/failover.lds
64 mainboardinit ./failover.inc
66 mainboardinit cpu/x86/fpu/enable_fpu.inc
67 mainboardinit cpu/x86/mmx/enable_mmx.inc
68 mainboardinit ./auto.inc
69 mainboardinit cpu/x86/mmx/disable_mmx.inc
74 chip northbridge/intel/i440bx # Northbridge
75 device apic_cluster 0 on # APIC cluster
76 chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually)
77 device apic 0 on end # APIC
80 device pci_domain 0 on # PCI domain
81 device pci 0.0 on end # Host bridge
82 device pci 1.0 on end # PCI/AGP bridge
83 chip southbridge/intel/i82371eb # Southbridge
84 device pci 7.0 on # ISA bridge
85 chip superio/winbond/w83627hf # Super I/O
86 device pnp 3f0.0 on # Floppy
91 device pnp 3f0.1 on # Parallel port
96 device pnp 3f0.2 on # COM1
100 device pnp 3f0.3 on # COM2 / IR
104 device pnp 3f0.5 on # PS/2 keyboard
107 irq 0x70 = 1 # PS/2 keyboard interrupt
108 irq 0x72 = 12 # PS/2 mouse interrupt
110 device pnp 3f0.6 on # Consumer IR
113 device pnp 3f0.7 on # Game port / MIDI / GPIO 1
118 device pnp 3f0.8 off # GPIO 2 / WDT
120 device pnp 3f0.9 off # GPIO 3
122 device pnp 3f0.a off # ACPI
124 device pnp 3f0.b off # HWM (TODO)
128 device pci 7.1 on end # IDE
129 device pci 7.2 on end # USB
130 device pci 7.3 on end # ACPI
131 device pci c.0 on end # Onboard audio (ES1371)
132 register "ide0_enable" = "1"
133 register "ide1_enable" = "1"
134 register "ide_legacy_enable" = "1"
135 # Enable UDMA/33 for higher speed if your IDE device(s) support it.
136 register "ide0_drive0_udma33_enable" = "0"
137 register "ide0_drive1_udma33_enable" = "0"
138 register "ide1_drive0_udma33_enable" = "0"
139 register "ide1_drive1_udma33_enable" = "0"