2 * This file is part of the coreboot project.
4 * Copyright (C) 2003 Eric Biederman
5 * Copyright (C) 2006-2010 coresystems GmbH
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 #include <pc80/mc146818rtc.h>
24 #if CONFIG_USE_OPTION_TABLE
25 #include "option_table.h"
27 #if !defined(__SMM__) && !defined(__PRE_RAM__)
28 #include <device/device.h>
31 /* Should support 8250, 16450, 16550, 16550A type UARTs */
33 static inline int uart8250_mem_can_tx_byte(unsigned base_port)
35 return read8(base_port + UART_LSR) & UART_MSR_DSR;
38 static inline void uart8250_mem_wait_to_tx_byte(unsigned base_port)
40 while(!uart8250_mem_can_tx_byte(base_port))
44 static inline void uart8250_mem_wait_until_sent(unsigned base_port)
46 while(!(read8(base_port + UART_LSR) & UART_LSR_TEMT))
50 void uart8250_mem_tx_byte(unsigned base_port, unsigned char data)
52 uart8250_mem_wait_to_tx_byte(base_port);
53 write8(base_port + UART_TBR, data);
54 /* Make certain the data clears the FIFOs */
55 uart8250_mem_wait_until_sent(base_port);
58 int uart8250_mem_can_rx_byte(unsigned base_port)
60 return read8(base_port + UART_LSR) & UART_LSR_DR;
63 unsigned char uart8250_mem_rx_byte(unsigned base_port)
65 while(!uart8250_mem_can_rx_byte(base_port))
67 return read8(base_port + UART_RBR);
70 void uart8250_mem_init(unsigned base_port, unsigned divisor)
72 /* Disable interrupts */
73 write8(base_port + UART_IER, 0x0);
75 write8(base_port + UART_FCR, UART_FCR_FIFO_EN);
77 /* Assert DTR and RTS so the other end is happy */
78 write8(base_port + UART_MCR, UART_MCR_DTR | UART_MCR_RTS);
81 write8(base_port + UART_LCR, UART_LCR_DLAB | CONFIG_TTYS0_LCS);
83 /* Set Baud Rate Divisor. 12 ==> 115200 Baud */
84 write8(base_port + UART_DLL, divisor & 0xFF);
85 write8(base_port + UART_DLM, (divisor >> 8) & 0xFF);
87 /* Set to 3 for 8N1 */
88 write8(base_port + UART_LCR, CONFIG_TTYS0_LCS);
91 u32 uart_mem_init(void)
93 unsigned uart_baud = CONFIG_TTYS0_BAUD;
97 /* find out the correct baud rate */
98 #if !defined(__SMM__) && CONFIG_USE_OPTION_TABLE
99 static const unsigned baud[8] = { 115200, 57600, 38400, 19200, 9600, 4800, 2400, 1200 };
100 unsigned b_index = 0;
101 #if defined(__PRE_RAM__)
102 b_index = read_option(CMOS_VSTART_baud_rate, CMOS_VLEN_baud_rate, 0);
104 uart_baud = baud[b_index];
106 if (get_option(&b_index, "baud_rate") == 0) {
107 uart_baud = baud[b_index];
112 /* Now find the UART base address and calculate the divisor */
113 #if CONFIG_DRIVERS_OXFORD_OXPCIE
115 #if defined(MORE_TESTING) && !defined(__SMM__) && !defined(__PRE_RAM__)
116 device_t dev = dev_find_device(0x1415, 0xc158, NULL);
119 struct resource *res = find_resource(dev, 0x10);
122 uart_bar = res->base + 0x1000; // for 1st UART
123 // uart_bar = res->base + 0x2000; // for 2nd UART
129 uart_bar = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000; // 1st UART
130 // uart_bar = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x2000; // 2nd UART
132 div = 4000000 / uart_baud;
136 uart8250_mem_init(uart_bar, div);