src/include/cpu/x86/smm.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008-2009 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 /* AMD64 SMM State-Save Area
  21  * starts @ 0x7e00
  22  */
  23
  24 #ifndef CPU_X86_SMM_H
  25 #define CPU_X86_SMM_H
  26
  27 /* used only by C programs so far */
  28 #define SMM_BASE 0xa0000
  29
  30 #include <types.h>
  31 typedef struct {
  32         u16     es_selector;
  33         u16     es_attributes;
  34         u32     es_limit;
  35         u64     es_base;
  36
  37         u16     cs_selector;
  38         u16     cs_attributcs;
  39         u32     cs_limit;
  40         u64     cs_base;
  41
  42         u16     ss_selector;
  43         u16     ss_attributss;
  44         u32     ss_limit;
  45         u64     ss_base;
  46
  47         u16     ds_selector;
  48         u16     ds_attributds;
  49         u32     ds_limit;
  50         u64     ds_base;
  51
  52         u16     fs_selector;
  53         u16     fs_attributfs;
  54         u32     fs_limit;
  55         u64     fs_base;
  56
  57         u16     gs_selector;
  58         u16     gs_attributgs;
  59         u32     gs_limit;
  60         u64     gs_base;
  61
  62         u8      reserved0[4];
  63         u16     gdtr_limit;
  64         u8      reserved1[2];
  65         u64     gdtr_base;
  66
  67         u16     ldtr_selector;
  68         u16     ldtr_attributes;
  69         u32     ldtr_limit;
  70         u64     ldtr_base;
  71
  72         u8      reserved2[4];
  73         u16     idtr_limit;
  74         u8      reserved3[2];
  75         u64     idtr_base;
  76
  77         u16     tr_selector;
  78         u16     tr_attributes;
  79         u32     tr_limit;
  80         u64     tr_base;
  81
  82         u8      reserved4[40];
  83
  84         u8      io_restart;
  85         u8      autohalt_restart;
  86
  87         u8      reserved5[6];
  88
  89         u64     efer;
  90
  91         u8      reserved6[36];
  92
  93         u32     smm_revision;
  94         u32     smbase;
  95
  96         u8      reserved7[68];
  97
  98         u64     cr4;
  99         u64     cr3;
 100         u64     cr0;
 101         u64     dr7;
 102         u64     dr6;
 103
 104         u64     rflags;
 105         u64     rip;
 106         u64     r15;
 107         u64     r14;
 108         u64     r13;
 109         u64     r12;
 110         u64     r11;
 111         u64     r10;
 112         u64     r9;
 113         u64     r8;
 114
 115         u64     rdi;
 116         u64     rsi;
 117         u64     rpb;
 118         u64     rsp;
 119         u64     rbx;
 120         u64     rdx;
 121         u64     rcx;
 122         u64     rax;
 123 } __attribute__((packed)) amd64_smm_state_save_area_t;
 124
 125
 126 /* Intel Core 2 (EM64T) SMM State-Save Area
 127  * starts @ 0x7d00
 128  */
 129 typedef struct {
 130         u8      reserved0[208];
 131
 132         u32     gdtr_upper_base;
 133         u32     ldtr_upper_base;
 134         u32     idtr_upper_base;
 135
 136         u8      reserved1[4];
 137
 138         u64     io_rdi;
 139         u64     io_rip;
 140         u64     io_rcx;
 141         u64     io_rsi;
 142         u64     cr4;
 143
 144         u8      reserved2[68];
 145
 146         u64     gdtr_base;
 147         u64     idtr_base;
 148         u64     ldtr_base;
 149
 150         u8      reserved3[84];
 151
 152         u32     smm_revision;
 153         u32     smbase;
 154
 155         u16     io_restart;
 156         u16     autohalt_restart;
 157
 158         u8      reserved4[24];
 159
 160         u64     r15;
 161         u64     r14;
 162         u64     r13;
 163         u64     r12;
 164         u64     r11;
 165         u64     r10;
 166         u64     r9;
 167         u64     r8;
 168
 169         u64     rax;
 170         u64     rcx;
 171         u64     rdx;
 172         u64     rbx;
 173
 174         u64     rsp;
 175         u64     rbp;
 176         u64     rsi;
 177         u64     rdi;
 178
 179
 180         u64     io_mem_addr;
 181         u32     io_misc_info;
 182
 183         u32     es_sel;
 184         u32     cs_sel;
 185         u32     ss_sel;
 186         u32     ds_sel;
 187         u32     fs_sel;
 188         u32     gs_sel;
 189
 190         u32     ldtr_sel;
 191         u32     tr_sel;
 192
 193         u64     dr7;
 194         u64     dr6;
 195         u64     rip;
 196         u64     efer;
 197         u64     rflags;
 198
 199         u64     cr3;
 200         u64     cr0;
 201 } __attribute__((packed)) em64t_smm_state_save_area_t;
 202
 203
 204 /* Legacy x86 SMM State-Save Area
 205  * starts @ 0x7e00
 206  */
 207
 208 typedef struct {
 209         u8      reserved0[248];
 210         u32     smbase;
 211         u32     smm_revision;
 212         u16     io_restart;
 213         u16     autohalt_restart;
 214         u8      reserved1[132];
 215         u32     gdtbase;
 216         u8      reserved2[8];
 217         u32     idtbase;
 218         u8      reserved3[16];
 219         u32     es;
 220         u32     cs;
 221         u32     ss;
 222         u32     ds;
 223         u32     fs;
 224         u32     gs;
 225         u32     ldtbase;
 226         u32     tr;
 227         u32     dr7;
 228         u32     dr6;
 229         u32     eax;
 230         u32     ecx;
 231         u32     edx;
 232         u32     ebx;
 233         u32     esp;
 234         u32     ebp;
 235         u32     esi;
 236         u32     edi;
 237         u32     eip;
 238         u32     eflags;
 239         u32     cr3;
 240         u32     cr0;
 241 } __attribute__((packed)) legacy_smm_state_save_area_t;
 242
 243 typedef enum {
 244         AMD64,
 245         EM64T,
 246         LEGACY
 247 } save_state_type_t;
 248
 249
 250 typedef struct {
 251         save_state_type_t type;
 252         union {
 253         amd64_smm_state_save_area_t *amd64_state_save;
 254         em64t_smm_state_save_area_t *em64t_state_save;
 255         legacy_smm_state_save_area_t *legacy_state_save;
 256         };
 257 } smm_state_save_area_t;
 258
 259 #define APM_CNT         0xb2
 260 #define APM_CNT_CST_CONTROL     0x85
 261 #define APM_CNT_PST_CONTROL     0x80
 262 #define APM_CNT_ACPI_DISABLE    0x1e
 263 #define APM_CNT_ACPI_ENABLE     0xe1
 264 #define APM_CNT_MBI_UPDATE      0xeb
 265 #define APM_CNT_GNVS_UPDATE     0xea
 266 #define APM_STS         0xb3
 267
 268 /* SMI handler function prototypes */
 269 void smi_handler(u32 smm_revision);
 270
 271 void io_trap_handler(int smif);
 272 int southbridge_io_trap_handler(int smif);
 273 int __attribute__((weak)) mainboard_io_trap_handler(int smif);
 274
 275 void southbridge_smi_set_eos(void);
 276
 277 void __attribute__((weak)) cpu_smi_handler(unsigned int node, smm_state_save_area_t *state_save);
 278 void __attribute__((weak)) northbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save);
 279 void __attribute__((weak)) southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save);
 280
 281 void __attribute__((weak)) mainboard_smi_gpi(u16 gpi_sts);
 282 int __attribute__((weak)) mainboard_apm_cnt(u8 data);
 283 #if !CONFIG_SMM_TSEG
 284 void smi_release_lock(void);
 285 #endif
 286
 287 #endif