src/include/cpu/x86/lapic.h

   1 #ifndef CPU_X86_LAPIC_H
   2 #define CPU_X86_LAPIC_H
   3
   4 #include <cpu/x86/lapic_def.h>
   5 #include <cpu/x86/msr.h>
   6 #include <arch/hlt.h>
   7
   8 /* See if I need to initialize the local apic */
   9 #if CONFIG_SMP || CONFIG_IOAPIC
  10 #  define NEED_LAPIC 1
  11 #endif
  12
  13 static inline __attribute__((always_inline)) unsigned long lapic_read(unsigned long reg)
  14 {
  15         return *((volatile unsigned long *)(LAPIC_DEFAULT_BASE+reg));
  16 }
  17
  18 static inline __attribute__((always_inline)) void lapic_write(unsigned long reg, unsigned long v)
  19 {
  20         *((volatile unsigned long *)(LAPIC_DEFAULT_BASE+reg)) = v;
  21 }
  22
  23 static inline __attribute__((always_inline)) void lapic_wait_icr_idle(void)
  24 {
  25         do { } while ( lapic_read( LAPIC_ICR ) & LAPIC_ICR_BUSY );
  26 }
  27
  28
  29
  30 static inline void enable_lapic(void)
  31 {
  32
  33         msr_t msr;
  34         msr = rdmsr(LAPIC_BASE_MSR);
  35         msr.hi &= 0xffffff00;
  36         msr.lo &= 0x000007ff;
  37         msr.lo |= LAPIC_DEFAULT_BASE | (1 << 11);
  38         wrmsr(LAPIC_BASE_MSR, msr);
  39 }
  40
  41 static inline void disable_lapic(void)
  42 {
  43         msr_t msr;
  44         msr = rdmsr(LAPIC_BASE_MSR);
  45         msr.lo &= ~(1 << 11);
  46         wrmsr(LAPIC_BASE_MSR, msr);
  47 }
  48
  49 static inline __attribute__((always_inline)) unsigned long lapicid(void)
  50 {
  51         return lapic_read(LAPIC_ID) >> 24;
  52 }
  53
  54 static inline __attribute__((always_inline)) void stop_this_cpu(void)
  55 {
  56
  57         unsigned apicid;
  58         apicid = lapicid();
  59
  60         /* Send an APIC INIT to myself */
  61         lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
  62         lapic_write(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT | LAPIC_DM_INIT);
  63         /* Wait for the ipi send to finish */
  64         lapic_wait_icr_idle();
  65
  66         /* Deassert the APIC INIT */
  67         lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
  68         lapic_write(LAPIC_ICR,  LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT);
  69         /* Wait for the ipi send to finish */
  70         lapic_wait_icr_idle();
  71
  72         /* If I haven't halted spin forever */
  73         for(;;) {
  74                 hlt();
  75         }
  76 }
  77
  78 #if ! defined (__ROMCC__)
  79
  80 #define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr))))
  81
  82 struct __xchg_dummy { unsigned long a[100]; };
  83 #define __xg(x) ((struct __xchg_dummy *)(x))
  84
  85 /*
  86  * Note: no "lock" prefix even on SMP: xchg always implies lock anyway
  87  * Note 2: xchg has side effect, so that attribute volatile is necessary,
  88  *        but generally the primitive is invalid, *ptr is output argument. --ANK
  89  */
  90 static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
  91 {
  92         switch (size) {
  93                 case 1:
  94                         __asm__ __volatile__("xchgb %b0,%1"
  95                                 :"=q" (x)
  96                                 :"m" (*__xg(ptr)), "0" (x)
  97                                 :"memory");
  98                         break;
  99                 case 2:
 100                         __asm__ __volatile__("xchgw %w0,%1"
 101                                 :"=r" (x)
 102                                 :"m" (*__xg(ptr)), "0" (x)
 103                                 :"memory");
 104                         break;
 105                 case 4:
 106                         __asm__ __volatile__("xchgl %0,%1"
 107                                 :"=r" (x)
 108                                 :"m" (*__xg(ptr)), "0" (x)
 109                                 :"memory");
 110                         break;
 111         }
 112         return x;
 113 }
 114
 115
 116 extern inline void lapic_write_atomic(unsigned long reg, unsigned long v)
 117 {
 118         xchg((volatile unsigned long *)(LAPIC_DEFAULT_BASE+reg), v);
 119 }
 120
 121
 122 #ifdef CONFIG_X86_GOOD_APIC
 123 # define FORCE_READ_AROUND_WRITE 0
 124 # define lapic_read_around(x) lapic_read(x)
 125 # define lapic_write_around(x,y) lapic_write((x),(y))
 126 #else
 127 # define FORCE_READ_AROUND_WRITE 1
 128 # define lapic_read_around(x) lapic_read(x)
 129 # define lapic_write_around(x,y) lapic_write_atomic((x),(y))
 130 #endif
 131
 132 static inline int lapic_remote_read(int apicid, int reg, unsigned long *pvalue)
 133 {
 134         int timeout;
 135         unsigned long status;
 136         int result;
 137         lapic_wait_icr_idle();
 138         lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
 139         lapic_write_around(LAPIC_ICR, LAPIC_DM_REMRD | (reg >> 4));
 140         timeout = 0;
 141         do {
 142 #if 0
 143                 udelay(100);
 144 #endif
 145                 status = lapic_read(LAPIC_ICR) & LAPIC_ICR_RR_MASK;
 146         } while (status == LAPIC_ICR_RR_INPROG && timeout++ < 1000);
 147
 148         result = -1;
 149         if (status == LAPIC_ICR_RR_VALID) {
 150                 *pvalue = lapic_read(LAPIC_RRR);
 151                 result = 0;
 152         }
 153         return result;
 154 }
 155
 156
 157 void setup_lapic(void);
 158
 159
 160 #if CONFIG_SMP == 1
 161 struct device;
 162 int start_cpu(struct device *cpu);
 163
 164 #endif /* CONFIG_SMP */
 165
 166
 167 #endif /* !__ROMCC__ */
 168
 169 #endif /* CPU_X86_LAPIC_H */