src/include/cpu/amd/gx2def.h

   1 #ifndef CPU_AMD_GX2DEF_H
   2 #define CPU_AMD_GX2DEF_H
   3
   4 #define CPU_ID_1_X                                                      0x540           /* Stepping ID 1.x*/
   5 #define CPU_ID_2_0                                                      0x551           /* Stepping ID 2.0*/
   6 #define CPU_ID_2_1                                                      0x552           /* Stepping ID 2.1*/
   7 #define CPU_ID_2_2                                                      0x553           /* Stepping ID 2.2*/
   8
   9 #define CPU_REV_1_0                                                     0x011
  10 #define CPU_REV_1_1                                                     0x012
  11 #define CPU_REV_1_2                                                     0x013
  12 #define CPU_REV_1_3                                                     0x014
  13 #define CPU_REV_2_0                                                     0x020
  14 #define CPU_REV_2_1                                                     0x021
  15 #define CPU_REV_2_2                                                     0x022
  16 #define CPU_REV_3_0                                                     0x030
  17
  18 /* GeodeLink Control Processor Registers, GLIU1, Port 3 */
  19 #define GLCP_CLK_DIS_DELAY      0x4c000008
  20 #define GLCP_PMCLKDISABLE       0x4c000009
  21 #define GLCP_CHIP_REVID         0x4c000017
  22
  23 /* GLCP_SYS_RSTPLL, Upper 32 bits */
  24 #define GLCP_SYS_RSTPLL_MDIV_SHIFT   9
  25 #define GLCP_SYS_RSTPLL_VDIV_SHIFT   6
  26 #define GLCP_SYS_RSTPLL_FBDIV_SHIFT  0
  27
  28 /* GLCP_SYS_RSTPLL, Lower 32 bits */
  29 #define GLCP_SYS_RSTPLL_SWFLAGS_SHIFT   26
  30 #define GLCP_SYS_RSTPLL_SWFLAGS_MASK    (0x3f << 26)
  31
  32 #define GLCP_SYS_RSTPLL_LOCKWAIT        24
  33 #define GLCP_SYS_RSTPLL_HOLDCOUNT       16
  34 #define GLCP_SYS_RSTPLL_BYPASS          15
  35 #define GLCP_SYS_RSTPLL_PD              14
  36 #define GLCP_SYS_RSTPLL_RESETPLL        13
  37 #define GLCP_SYS_RSTPLL_DDRMODE         10
  38 #define GLCP_SYS_RSTPLL_VA_SEMI_SYNC_MODE   9
  39 #define GLCP_SYS_RSTPLL_PCI_SEMI_SYNC_MODE  8
  40 #define GLCP_SYS_RSTPLL_CHIP_RESET          0
  41
  42 /* MSR routing as follows */
  43 /* MSB = 1 means not for CPU */
  44 /* next 3 bits 1st port */
  45 /* next3 bits next port if through an GLIU */
  46 /* etc... */
  47
  48 /* Redcloud as follows. */
  49 /* GLIU0*/
  50 /*      port0 - GLIU0 */
  51 /*      port1 - MC */
  52 /*      port2 - GLIU1 */
  53 /*      port3 - CPU */
  54 /*      port4 - VG */
  55 /*      port5 - GP */
  56 /*      port6 - DF */
  57
  58 /* GLIU1*/
  59 /*      port1 - GLIU0 */
  60 /*      port3 - GLCP */
  61 /*      port4 - PCI */
  62 /*      port5 - FG */
  63
  64 #define GL0_GLIU0                       0
  65 #define GL0_MC                          1
  66 #define GL0_GLIU1                       2
  67 #define GL0_CPU                         3
  68 #define GL0_VG                          4
  69 #define GL0_GP                          5
  70 #define GL0_DF                          6
  71
  72 #define GL1_GLIU0                       1
  73 #define GL1_GLCP                        3
  74 #define GL1_PCI                         4
  75 #define GL1_FG                          5
  76 #define GL1_VIP                         5
  77 #define GL1_AES                         6
  78
  79 #define MSR_GLIU0                       (GL0_GLIU0 << 29) + (1 << 28)   /* 1000xxxx - To get on GeodeLink one bit has to be set */
  80 #define MSR_MC                          (GL0_MC         << 29)  /* 2000xxxx */
  81 #define MSR_GLIU1                       (GL0_GLIU1      << 29)  /* 4000xxxx */
  82 #define MSR_CPU                         (GL0_CPU        << 29)  /* 6000xxxx - this is not used for BIOS since code executing on CPU doesn't need to be routed */
  83 #define MSR_VG                          (GL0_VG         << 29)  /* 8000xxxx */
  84 #define MSR_GP                          (GL0_GP         << 29)  /* A000xxxx */
  85 #define MSR_DF                          (GL0_DF         << 29)  /* C000xxxx */
  86
  87 #define MSR_GLCP                        (GL1_GLCP << 26) + MSR_GLIU1    /* 4C00xxxx */
  88 #define MSR_PCI                         (GL1_PCI << 26) + MSR_GLIU1     /* 5000xxxx */
  89 #define MSR_FG                          (GL1_FG << 26) + MSR_GLIU1      /* 5400xxxx */
  90 #define MSR_VIP                         ((GL1_VIP << 26) + MSR_GLIU1)   /* 5400xxxx */
  91 #define MSR_AES                         ((GL1_AES << 26) + MSR_GLIU1)   /* 5800xxxx */
  92
  93 /* South Bridge */
  94 #define SB_PORT 2                       /* port of the SouthBridge */
  95
  96 /* GeodeLink Interface Unit 0 (GLIU0) port0 */
  97 #define GLIU0_GLD_MSR_CAP                       (MSR_GLIU0 + 0x2000)
  98 #define GLIU0_GLD_MSR_PM                        (MSR_GLIU0 + 0x2004)
  99
 100 #define GLIU0_DESC_BASE                         (MSR_GLIU0 + 0x20)
 101 #define GLIU0_CAP                                       (MSR_GLIU0 + 0x86)
 102 #define GLIU0_GLD_MSR_COH                       (MSR_GLIU0 + 0x80)
 103
 104 /* Memory Controller GLIU0 port 1 */
 105 #define MC_GLD_MSR_CAP                  (MSR_MC + 0x2000)
 106 #define MC_GLD_MSR_PM                   (MSR_MC + 0x2004)
 107
 108 #define MC_CF07_DATA                    (MSR_MC + 0x18)
 109
 110 #define         CF07_UPPER_D1_SZ_SHIFT                          28
 111 #define         CF07_UPPER_D1_MB_SHIFT                          24
 112 #define         CF07_UPPER_D1_CB_SHIFT                          20
 113 #define         CF07_UPPER_D1_PSZ_SHIFT                         16
 114 #define         CF07_UPPER_D0_SZ_SHIFT                          12
 115 #define         CF07_UPPER_D0_MB_SHIFT                          8
 116 #define         CF07_UPPER_D0_CB_SHIFT                          4
 117 #define         CF07_UPPER_D0_PSZ_SHIFT                         0
 118
 119 #define         CF07_LOWER_REF_INT_SHIFT                                8
 120 #define         CF07_LOWER_LOAD_MODE_DDR_SET            (1 << 28)
 121 #define         CF07_LOWER_LOAD_MODE_DLL_RESET          (1 << 27)
 122 #define         CF07_LOWER_EMR_QFC_SET                          (1 << 26)
 123 #define         CF07_LOWER_EMR_DRV_SET                          (1 << 25)
 124 #define         CF07_LOWER_REF_TEST_SET                         (1 << 3)
 125 #define         CF07_LOWER_PROG_DRAM_SET                        (1 << 0)
 126
 127 #define MC_CF8F_DATA                    (MSR_MC + 0x19)
 128
 129 #define         CF8F_UPPER_XOR_BS_SHIFT                         19
 130 #define         CF8F_UPPER_XOR_MB0_SHIFT                        18
 131 #define         CF8F_UPPER_XOR_BA1_SHIFT                        17
 132 #define         CF8F_UPPER_XOR_BA0_SHIFT                        16
 133 #define         CF8F_UPPER_REORDER_DIS_SET              (1 << 8)
 134 #define         CF8F_UPPER_REG_DIMM_SHIFT                       4
 135 #define         CF8F_LOWER_CAS_LAT_SHIFT                        28
 136 #define         CF8F_LOWER_REF2ACT_SHIFT                        24
 137 #define         CF8F_LOWER_ACT2PRE_SHIFT                        20
 138 #define         CF8F_LOWER_PRE2ACT_SHIFT                        16
 139 #define         CF8F_LOWER_ACT2CMD_SHIFT                        12
 140 #define         CF8F_LOWER_ACT2ACT_SHIFT                        8
 141 #define         CF8F_UPPER_32BIT_SET                            (1 << 5)
 142 #define         CF8F_UPPER_HOI_LOI_SET                  (1 << 1)
 143
 144 #define MC_CF1017_DATA                  (MSR_MC + 0x1A)
 145
 146 #define         CF1017_LOWER_PM1_UP_DLY_SET                     (1 << 8)
 147 #define         CF1017_LOWER_WR2DAT_SHIFT                       0
 148
 149 #define MC_CFCLK_DBUG                   (MSR_MC + 0x1D)
 150
 151 #define         CFCLK_UPPER_MTST_B2B_DIS_SET                    (1 << 2)
 152 #define         CFCLK_UPPER_MTST_DQS_EN_SET                     (1 << 1)
 153 #define         CFCLK_UPPER_MTEST_EN_SET                                (1 << 0)
 154
 155 #define         CFCLK_LOWER_MASK_CKE_SET1                       (1 << 9)
 156 #define         CFCLK_LOWER_MASK_CKE_SET0                       (1 << 8)
 157 #define         CFCLK_LOWER_SDCLK_SET                           (0x0F << 0)
 158
 159 #define MC_CF_RDSYNC                    (MSR_MC + 0x1F)
 160
 161 /* GLIU1 GLIU0 port2 */
 162 #define GLIU1_GLD_MSR_CAP                       (MSR_GLIU1 + 0x2000)
 163 #define GLIU1_GLD_MSR_PM                        (MSR_GLIU1 + 0x2004)
 164
 165 #define GLIU1_GLD_MSR_COH                       (MSR_GLIU1 + 0x80)
 166
 167 /* CPU  ; does not need routing instructions since we are executing there. */
 168 #define CPU_GLD_MSR_CAP                                         0x2000
 169 #define CPU_GLD_MSR_CONFIG                                      0x2001
 170 #define CPU_GLD_MSR_PM                                          0x2004
 171
 172 #define CPU_GLD_MSR_DIAG                                        0x2005
 173 #define         DIAG_SEL1_MODE_SHIFT                            16
 174 #define         DIAG_SEL1_SET                                           (1 << 31)
 175 #define         DIAG_SEL0__MODE_SHIFT                           0
 176 #define         DIAG_SET0_SET                                           (1 << 15)
 177
 178 #define CPU_PF_BTB_CONF                                         0x1100
 179 #define         BTB_ENABLE_SET                                          (1 << 0)
 180 #define         RETURN_STACK_ENABLE_SET                         (1 << 4)
 181 #define CPU_PF_BTBRMA_BIST                                      0x110C
 182
 183 #define CPU_XC_CONFIG                                           0x1210
 184 #define         XC_CONFIG_SUSP_ON_HLT                           (1 << 0)
 185 #define CPU_ID_CONFIG                                           0x1250
 186 #define         ID_CONFIG_SERIAL_SET                            (1 << 0)
 187
 188 #define CPU_AC_MSR                                                      0x1301
 189 #define CPU_EX_BIST                                                     0x1428
 190
 191 /* IM */
 192 #define CPU_IM_CONFIG                                                   0x1700
 193 #define         IM_CONFIG_LOWER_ICD_SET                                 (1 << 8)
 194 #define         IM_CONFIG_LOWER_QWT_SET                                 (1 << 20)
 195 #define CPU_IC_INDEX                                                    0x1710
 196 #define CPU_IC_DATA                                                             0x1711
 197 #define CPU_IC_TAG                                                              0x1712
 198 #define CPU_IC_TAG_I                                                    0x1713
 199 #define CPU_ITB_INDEX                                                   0x1720
 200 #define CPU_ITB_LRU                                                             0x1721
 201 #define CPU_ITB_ENTRY                                                   0x1722
 202 #define CPU_ITB_ENTRY_I                                                 0x1723
 203 #define CPU_IM_BIST_TAG                                                 0x1730
 204 #define CPU_IM_BIST_DATA                                                0x1731
 205
 206 /* various CPU MSRs */
 207 #define CPU_DM_CONFIG0 0x1800
 208 #define DM_CONFIG0_UPPER_WSREQ_SHIFT  12
 209 #define DM_CONFIG0_LOWER_DCDIS_SET              (1<<8)
 210 #define DM_CONFIG0_LOWER_WBINVD_SET     (1<<5)
 211 #define DM_CONFIG0_LOWER_MISSER_SET             (1<<1)
 212
 213 /* configuration MSRs */
 214 #define CPU_RCONF_DEFAULT                                               0x1808
 215 #define         RCONF_DEFAULT_UPPER_ROMRC_SHIFT                         24
 216 #define         RCONF_DEFAULT_UPPER_ROMBASE_SHIFT                       4
 217 #define         RCONF_DEFAULT_UPPER_DEVRC_HI_SHIFT                      0
 218 #define         RCONF_DEFAULT_LOWER_DEVRC_LOW_SHIFT                     28
 219 #define         RCONF_DEFAULT_LOWER_SYSTOP_SHIFT                        8
 220 #define         RCONF_DEFAULT_LOWER_SYSRC_SHIFT                         0
 221
 222 #define CPU_RCONF_BYPASS                                                0x180A
 223 #define CPU_RCONF_A0_BF                                                 0x180B
 224 #define CPU_RCONF_C0_DF                                                 0x180C
 225 #define CPU_RCONF_E0_FF                                                 0x180D
 226
 227 #define CPU_RCONF_SMM                                                   0x180E
 228 #define         RCONF_SMM_UPPER_SMMTOP_SHIFT                    12
 229 #define         RCONF_SMM_UPPER_RCSMM_SHIFT                             0
 230 #define         RCONF_SMM_LOWER_SMMBASE_SHIFT                   12
 231 #define         RCONF_SMM_LOWER_RCNORM_SHIFT                    0
 232 #define         RCONF_SMM_LOWER_EN_SET                                  (1<<8)
 233
 234 #define CPU_RCONF_DMM                                                   0x180F
 235 #define         RCONF_DMM_UPPER_DMMTOP_SHIFT                    12
 236 #define         RCONF_DMM_UPPER_RCDMM_SHIFT                             0
 237 #define         RCONF_DMM_LOWER_DMMBASE_SHIFT                   12
 238 #define         RCONF_DMM_LOWER_RCNORM_SHIFT                    0
 239 #define         RCONF_DMM_LOWER_EN_SET                                  (1<<8)
 240
 241 #define CPU_RCONF0                                                      0x1810
 242 #define CPU_RCONF1                                                      0x1811
 243 #define CPU_RCONF2                                                      0x1812
 244 #define CPU_RCONF3                                                      0x1813
 245 #define CPU_RCONF4                                                      0x1814
 246 #define CPU_RCONF5                                                      0x1815
 247 #define CPU_RCONF6                                                      0x1816
 248 #define CPU_RCONF7                                                      0x1817
 249 #define CPU_CR1_MSR                                                     0x1881
 250 #define CPU_CR2_MSR                                                     0x1882
 251 #define CPU_CR3_MSR                                                     0x1883
 252 #define CPU_CR4_MSR                                                     0x1884
 253 #define CPU_DC_INDEX                                            0x1890
 254 #define CPU_DC_DATA                                                     0x1891
 255 #define CPU_DC_TAG                                                      0x1892
 256 #define CPU_DC_TAG_I                                            0x1893
 257 #define CPU_SNOOP                                                       0x1894
 258 #define CPU_DTB_INDEX                                           0x1898
 259 #define CPU_DTB_LRU                                                     0x1899
 260 #define CPU_DTB_ENTRY                                           0x189A
 261 #define CPU_DTB_ENTRY_I                                         0x189B
 262 #define CPU_L2TB_INDEX                                          0x189C
 263 #define CPU_L2TB_LRU                                            0x189D
 264 #define CPU_L2TB_ENTRY                                          0x189E
 265 #define CPU_L2TB_ENTRY_I                                        0x189F
 266 #define CPU_DM_BIST                                                     0x18C0
 267                 /* SMM */
 268 #define CPU_AC_SMM_CTL                                          0x1301
 269 #define         SMM_NMI_EN_SET                                  (1<<0)
 270 #define         SMM_SUSP_EN_SET                                 (1<<1)
 271 #define         NEST_SMI_EN_SET                                 (1<<2)
 272 #define         SMM_INST_EN_SET                                 (1<<3)
 273 #define         INTL_SMI_EN_SET                                 (1<<4)
 274 #define         EXTL_SMI_EN_SET                                 (1<<5)
 275
 276 #define CPU_FPU_MSR_MODE                                        0x1A00
 277 #define         FPU_IE_SET                                              (1<<0)
 278
 279 #define CPU_FP_UROM_BIST                                        0x1A03
 280
 281 #define CPU_BC_CONF_0                                           0x1900
 282 #define         TSC_SUSP_SET                             (1<<5)
 283 #define         SUSP_EN_SET                              (1<<12)
 284
 285 /* VG GLIU0 port4 */
 286 #define VG_GLD_MSR_CAP                          (MSR_VG + 0x2000)
 287 #define VG_GLD_MSR_CONFIG                       (MSR_VG + 0x2001)
 288 #define VG_GLD_MSR_PM                           (MSR_VG + 0x2004)
 289
 290 #define GP_GLD_MSR_CAP                          (MSR_GP + 0x2000)
 291 #define GP_GLD_MSR_CONFIG                       (MSR_GP + 0x2001)
 292 #define GP_GLD_MSR_PM                           (MSR_GP + 0x2004)
 293
 294 /* DF GLIU0 port6 */
 295 #define DF_GLD_MSR_CAP                                  (MSR_DF + 0x2000)
 296 #define DF_GLD_MSR_MASTER_CONF                  (MSR_DF + 0x2001)
 297 #define         DF_LOWER_LCD_SHIFT                              6
 298 #define DF_GLD_MSR_PM                                   (MSR_DF + 0x2004)
 299
 300 /* GeodeLink Control Processor GLIU1 port3 */
 301 #define GLCP_GLD_MSR_CAP                        (MSR_GLCP + 0x2000)
 302 #define GLCP_GLD_MSR_CONF                       (MSR_GLCP + 0x2001)
 303 #define GLCP_GLD_MSR_PM                         (MSR_GLCP + 0x2004)
 304
 305 #define GLCP_DELAY_CONTROLS                     (MSR_GLCP + 0x0F)
 306
 307 #define GLCP_SYS_RSTPLL                         (MSR_GLCP +0x14 /* R/W */)
 308 #define         RSTPLL_UPPER_MDIV_SHIFT                         9
 309 #define         RSTPLL_UPPER_VDIV_SHIFT                         6
 310 #define         RSTPLL_UPPER_FBDIV_SHIFT                        0
 311
 312 #define         RSTPLL_LOWER_SWFLAGS_SHIFT                      26
 313 #define         RSTPLL_LOWER_SWFLAGS_MASK                       (0x3F<<RSTPLL_LOWER_SWFLAGS_SHIFT)
 314
 315 #define         RSTPPL_LOWER_HOLD_COUNT_SHIFT                   16
 316 #define         RSTPPL_LOWER_BYPASS_SHIFT                       15
 317 #define         RSTPPL_LOWER_TST_SHIFT                          11
 318 #define         RSTPPL_LOWER_SDRMODE_SHIFT               10
 319 #define         RSTPPL_LOWER_BOOTSTRAP_SHIFT             4
 320
 321 #define         RSTPPL_LOWER_LOCK_SET                           (1<<25)
 322 #define         RSTPPL_LOWER_LOCKWAIT_SET                       (1<<24)
 323 #define         RSTPPL_LOWER_BYPASS_SET                         (1<<15)
 324 #define         RSTPPL_LOWER_PD_SET                                     (1<<14)
 325 #define         RSTPPL_LOWER_PLL_RESET_SET                      (1<<13)
 326 #define         RSTPPL_LOWER_SDRMODE_SET                 (1<<10)
 327 #define         RSTPPL_LOWER_CPU_SEMI_SYNC_SET           (1<<9)
 328 #define         RSTPPL_LOWER_PCI_SEMI_SYNC_SET           (1<<8)
 329 #define         RSTPPL_LOWER_CHIP_RESET_SET              (1<<0)
 330
 331 #define GLCP_DOTPLL                             (MSR_GLCP + 0x15        /* R/W */)
 332 #define         DOTPPL_LOWER_PD_SET                              (1<<14)
 333
 334 /* GLIU1 port 4 */
 335 #define GLPCI_GLD_MSR_CAP                       (MSR_PCI + 0x2000)
 336 #define GLPCI_GLD_MSR_CONFIG                    (MSR_PCI + 0x2001)
 337 #define GLPCI_GLD_MSR_PM                                (MSR_PCI + 0x2004)
 338
 339 #define GLPCI_CTRL                      (MSR_PCI + 0x2010)
 340 #define GLPCI_CTRL_UPPER_FTH_SHIFT                              28
 341 #define GLPCI_CTRL_UPPER_RTH_SHIFT                              24
 342 #define GLPCI_CTRL_UPPER_SBRTH_SHIFT                            20
 343 #define GLPCI_CTRL_UPPER_DTL_SHIFT                              14
 344 #define GLPCI_CTRL_UPPER_WTO_SHIFT                              11
 345 #define GLPCI_CTRL_UPPER_LAT_SHIFT                              3
 346 #define GLPCI_CTRL_UPPER_ILTO_SHIFT                             8
 347 #define GLPCI_CTRL_LOWER_IRFT_SHIFT                             18
 348 #define GLPCI_CTRL_LOWER_IRFC_SHIFT                             16
 349 #define GLPCI_CTRL_LOWER_ER_SET                                 (1<<11)
 350 #define GLPCI_CTRL_LOWER_LDE_SET                                        (1<<9)
 351 #define GLPCI_CTRL_LOWER_OWC_SET                                        (1<<4)
 352 #define GLPCI_CTRL_LOWER_IWC_SET                                        (1<<3)
 353 #define GLPCI_CTRL_LOWER_PCD_SET                                        (1<<2)
 354 #define GLPCI_CTRL_LOWER_ME_SET                                 (1<<0)
 355
 356 #define GLPCI_ARB                       (MSR_PCI + 0x2011)
 357 #define GLPCI_ARB_UPPER_BM1_SET                                 (1<<17)
 358 #define GLPCI_ARB_UPPER_BM0_SET                                 (1<<16)
 359 #define GLPCI_ARB_UPPER_CPRE_SET                                        (1<<15)
 360 #define GLPCI_ARB_UPPER_PRE2_SET                                        (1<<10)
 361 #define GLPCI_ARB_UPPER_PRE1_SET                                        (1<<9)
 362 #define GLPCI_ARB_UPPER_PRE0_SET                                        (1<<8)
 363 #define GLPCI_ARB_UPPER_CRME_SET                                        (1<<7)
 364 #define GLPCI_ARB_UPPER_RME2_SET                                        (1<<2)
 365 #define GLPCI_ARB_UPPER_RME1_SET                                        (1<<1)
 366 #define GLPCI_ARB_UPPER_RME0_SET                                        (1<<0)
 367 #define GLPCI_ARB_LOWER_PRCM_SHIFT                              24
 368 #define GLPCI_ARB_LOWER_FPVEC_SHIFT                             16
 369 #define GLPCI_ARB_LOWER_RMT_SHIFT                               6
 370 #define GLPCI_ARB_LOWER_IIE_SET                                 (1<<8)
 371 #define GLPCI_ARB_LOWER_PARK_SET                                        (1<<0)
 372
 373 #define GLPCI_REN                       (MSR_PCI + 0x2014)
 374 #define GLPCI_A0_BF                     (MSR_PCI + 0x2015)
 375 #define GLPCI_C0_DF                     (MSR_PCI + 0x2016)
 376 #define GLPCI_E0_FF                     (MSR_PCI + 0x2017)
 377 #define GLPCI_RC0                       (MSR_PCI + 0x2018)
 378 #define GLPCI_RC1                       (MSR_PCI + 0x2019)
 379 #define GLPCI_RC2                       (MSR_PCI + 0x201A)
 380 #define GLPCI_RC3                       (MSR_PCI + 0x201B)
 381 #define GLPCI_RC4                       (MSR_PCI + 0x201C)
 382 #define         GLPCI_RC_UPPER_TOP_SHIFT                                12
 383 #define         GLPCI_RC_LOWER_BASE_SHIFT                       12
 384 #define         GLPCI_RC_LOWER_EN_SET                           (1<<8)
 385 #define         GLPCI_RC_LOWER_PF_SET                           (1<<5)
 386 #define         GLPCI_RC_LOWER_WC_SET                           (1<<4)
 387 #define         GLPCI_RC_LOWER_WP_SET                           (1<<2)
 388 #define         GLPCI_RC_LOWER_CD_SET                           (1<<0)
 389 #define GLPCI_ExtMSR                    (MSR_PCI + 0x201E)
 390 #define GLPCI_SPARE                     (MSR_PCI + 0x201F)
 391 #define         GLPCI_SPARE_LOWER_AILTO_SET                                     (1<<6)
 392 #define         GLPCI_SPARE_LOWER_PPD_SET                                       (1<<5)
 393 #define         GLPCI_SPARE_LOWER_PPC_SET                                       (1<<4)
 394 #define         GLPCI_SPARE_LOWER_MPC_SET                                       (1<<3)
 395 #define         GLPCI_SPARE_LOWER_MME_SET                                       (1<<2)
 396 #define         GLPCI_SPARE_LOWER_NSE_SET                                       (1<<1)
 397 #define         GLPCI_SPARE_LOWER_SUPO_SET                                      (1<<0)
 398
 399 /* FooGlue GLIU1 port 5 */
 400 #define FG_GLD_MSR_CAP                  (MSR_FG + 0x2000)
 401 #define FG_GLD_MSR_PM                   (MSR_FG + 0x2004)
 402
 403 /* VIP GLIU1 port 5 */
 404 #define VIP_GLD_MSR_CAP         (MSR_VIP + 0x2000)
 405 #define VIP_GLD_MSR_CONFIG      (MSR_VIP + 0x2001)
 406 #define VIP_GLD_MSR_PM          (MSR_VIP + 0x2004)
 407 #define VIP_BIST                (MSR_VIP + 0x2005)
 408 #define VIP_GIO_MSR_SEL         (MSR_VIP + 0x2010)
 409
 410 /* AES GLIU1 port 6 */
 411 #define AES_GLD_MSR_CAP         (MSR_AES + 0x2000)
 412 #define AES_GLD_MSR_CONFIG      (MSR_AES + 0x2001)
 413 #define AES_GLD_MSR_PM          (MSR_AES + 0x2004)
 414 #define AES_CONTROL             (MSR_AES + 0x2006)
 415
 416 /* from MC spec */
 417 #define MIN_MOD_BANKS           1
 418 #define MAX_MOD_BANKS           2
 419 #define MIN_DEV_BANKS           2
 420 #define MAX_DEV_BANKS           4
 421 #define MAX_COL_ADDR            17
 422
 423 /* more fun stuff */
 424 #define BM                      1       /* Base Mask - map power of 2 size aligned region */
 425 #define BMO                     2       /* BM with an offset */
 426 #define R                               3       /* Range - 4k range minimum */
 427 #define RO                      4       /* R with offset */
 428 #define SC                      5       /* Swiss 0xCeese - maps a 256K region in to 16K 0xcunks. Set W/R */
 429 #define BMIO                    6       /* Base Mask IO */
 430 #define SCIO                    7       /* Swiss 0xCeese IO */
 431 #define SC_SHADOW       8       /* Special marker for Shadow SC descriptors so setShadow proc is independant of CPU */
 432 #define R_SYSMEM                9       /* Special marker for SYSMEM R descriptors so GLIUInit proc is independant of CPU */
 433 #define BMO_SMM         10      /* Specail marker for SMM */
 434 #define BM_SMM          11      /* Specail marker for SMM */
 435 #define BMO_DMM         12      /* Specail marker for DMM */
 436 #define BM_DMM          13      /* Specail marker for DMM */
 437 #define RO_FB                   14      /* special for Frame buffer. */
 438 #define R_FB                    15      /* special for FB. */
 439 #define OTHER                   0x0FE /* Special marker for other */
 440 #define GL_END           0x0FF  /* end */
 441
 442 #define MSR_GL0 (GL1_GLIU0 << 29)
 443
 444 /* Set up desc addresses from 20 - 3f */
 445 /* This is chip specific! */
 446 #define MSR_GLIU0_BASE1                 (MSR_GLIU0 + 0x20)              /* BM */
 447 #define MSR_GLIU0_BASE2                 (MSR_GLIU0 + 0x21)              /* BM */
 448 #define MSR_GLIU0_SHADOW                        (MSR_GLIU0 + 0x2C)              /* SCO should only be SC */
 449 #define MSR_GLIU0_SYSMEM                        (MSR_GLIU0 + 0x28)              /* RO should only be R */
 450 #define MSR_GLIU0_SMM                   (MSR_GLIU0 + 0x26)              /* BMO */
 451 #define MSR_GLIU0_DMM                   (MSR_GLIU0 + 0x27)              /* BMO */
 452
 453 #define MSR_GLIU1_BASE1                 (MSR_GLIU1 + 0x20)              /* BM */
 454 #define MSR_GLIU1_BASE2                 (MSR_GLIU1 + 0x21)              /* BM */
 455 #define MSR_GLIU1_SHADOW                        (MSR_GLIU1 + 0x2D)              /* SCO should only be SC */
 456 #define MSR_GLIU1_SYSMEM                        (MSR_GLIU1 + 0x29)              /* RO should only be R */
 457 #define MSR_GLIU1_SMM                   (MSR_GLIU1 + 0x23)              /* BM */
 458 #define MSR_GLIU1_DMM                   (MSR_GLIU1 + 0x24)              /* BM */
 459 #define MSR_GLIU1_FPU_TRAP              (MSR_GLIU1 + 0x0E3)     /* FooGlue F0 for FPU */
 460
 461 /* definitions that are "once you are mostly up, start VSA" type things */
 462 #define SMM_OFFSET      0x40400000
 463 #define SMM_SIZE                128                     /* changed SMM_SIZE from 256 KB to 128 KB */
 464 #define DMM_OFFSET      0x0C0000000
 465 #define DMM_SIZE                128
 466 #define FB_OFFSET               0x41000000
 467 #define PCI_MEM_TOP     0x0EFFFFFFF      // Top of PCI mem allocation region
 468 #define PCI_IO_TOP              0x0EFFF          // Top of PCI I/O allocation region
 469 #define END_OPTIONROM_SPACE     0x0DFFF          // E0000 is reserved for SystemROMs.
 470
 471 #define MDD_SMBUS       0x06000          // SMBUS IO location
 472 #define MDD_GPIO                0x06100          // GPIO & ICF IO location
 473 #define MDD_MFGPT       0x06200          // General Purpose Timers IO location
 474 #define MDD_IRQ_MAPPER  0x06300          // IRQ Mapper
 475 #define ACPI_BASE               0x09C00          // ACPI Base
 476 #define MDD_PM          0x09D00          // Power Management Logic - placed at the end of ACPI
 477
 478 #define CS5535_IDSEL    0x02000000       // IDSEL = AD25, device #15
 479 #define CHIPSET_DEV_NUM 15
 480 #define IDSEL_BASE      11                       // bit 11 = device 1
 481
 482 /* SB LBAR IO + MEMORY MAP */
 483 #define SMBUS_BASE               (              0x6000)
 484 #define GPIO_BASE                (              0x6100)
 485 #define MFGPT_BASE               (              0x6200)
 486 #define IRQMAP_BASE              (              0x6300)
 487 #define PMLogic_BASE     (              0x9D00)
 488
 489
 490 #if !defined(__ROMCC__)  && !defined(ASSEMBLY)
 491 #if defined(__PRE_RAM__)
 492 void cpuRegInit(void);
 493 void SystemPreInit(void);
 494 #endif
 495 void cpubug(void);
 496 #endif
 497
 498 #endif /* CPU_AMD_GX2DEF_H */