2 freebios/src/northbridge/nsc/gx1/gx1def.inc
4 Copyright (c) 2002 Christer Weinigel <wingel@hack.org>
6 Defines for the GX1 processor
8 /* now adapted for the gx2 by rminnich@lanl.gov
11 #define GX_BASE 0x040000000
13 /**********************************************************************/
14 /* Display Controller Registers, offset from GX_BASE */
16 #define DC_UNLOCK 0x8300
17 #define DC_UNLOCK_MAGIC 0x4758
19 #define DC_GENERAL_CFG 0x8304
21 /**********************************************************************/
22 /* Bus Controller Registers, offset from GX_BASE */
24 #define BC_DRAM_TOP 0x8000
26 #define BC_XMAP_1 0x8004
27 #define BC_XMAP_2 0x8008
28 #define BC_XMAP_3 0x800c
30 /**********************************************************************/
31 /* Memory Controller Registers, offset from GX_BASE */
33 #define MC_MEM_CNTRL1 0x8400
34 #define SDCLKSTRT (1<<17)
35 #define RFSHRATE (0x1ff<<8)
36 #define RFSHSTAG (0x3<<6)
37 #define X2CLKADDR (1<<5)
38 #define RFSHTST (1<<4)
39 #define XBUSARB (1<<3)
40 #define SMM_MAP (1<<2)
41 #define PROGRAM_SDRAM (1<<0)
43 #define MC_MEM_CNTRL2 0x8404
44 #define SDCLK_MASK 0x000003c0
45 #define SDCLKOUT_MASK 0x00000400
47 #define MC_BANK_CFG 0x8408
48 #define DIMM_PG_SZ 0x00000070
49 #define DIMM_SZ 0x00000700
50 #define DIMM_COMP_BNK 0x00001000
51 #define DIMM_MOD_BNK 0x00004000
53 #define MC_SYNC_TIM1 0x840c
55 #define MC_GBASE_ADD 0x8414