1 #ifndef CPU_AMD_GX2DEF_H
2 #define CPU_AMD_GX2DEF_H
4 #define CPU_ID_1_X 0x540 /* Stepping ID 1.x*/
5 #define CPU_ID_2_0 0x551 /* Stepping ID 2.0*/
6 #define CPU_ID_2_1 0x552 /* Stepping ID 2.1*/
7 #define CPU_ID_2_2 0x553 /* Stepping ID 2.2*/
9 #define CPU_REV_1_0 0x011
10 #define CPU_REV_1_1 0x012
11 #define CPU_REV_1_2 0x013
12 #define CPU_REV_1_3 0x014
13 #define CPU_REV_2_0 0x020
14 #define CPU_REV_2_1 0x021
15 #define CPU_REV_2_2 0x022
16 #define CPU_REV_3_0 0x030
18 /* GeodeLink Control Processor Registers, GLIU1, Port 3 ; MSR_GLCP = 4c00xxxx */
19 #define GLCP_CLK_DIS_DELAY (MSR_GLCP + 0x08)
20 #define GLCP_PMCLKDISABLE (MSR_GLCP + 0x09)
21 #define GLCP_DBGOUT (MSR_GLCP + 0x0C)
22 #define GLCP_PROCSTAT (MSR_GLCP + 0x0D)
23 #define GLCP_DBGCLKCTL (MSR_GLCP + 0x16)
24 #define GLCP_CHIP_REVID (MSR_GLCP + 0x17)
25 #define GLCP_TH_OD (MSR_GLCP + 0x1E)
26 #define GLCP_FIFOCTL (MSR_GLCP + 0x5E)
28 /* GLCP_SYS_RSTPLL, Upper 32 bits */
29 #define GLCP_SYS_RSTPLL_MDIV_SHIFT 9
30 #define GLCP_SYS_RSTPLL_VDIV_SHIFT 6
31 #define GLCP_SYS_RSTPLL_FBDIV_SHIFT 0
33 /* GLCP_SYS_RSTPLL, Lower 32 bits */
34 #define GLCP_SYS_RSTPLL_SWFLAGS_SHIFT 26
35 #define GLCP_SYS_RSTPLL_SWFLAGS_MASK (0x3f << 26)
36 #define GLCP_SYS_RSTPLL_LOCKWAIT 24
37 #define GLCP_SYS_RSTPLL_HOLDCOUNT 16
38 #define GLCP_SYS_RSTPLL_BYPASS 15
39 #define GLCP_SYS_RSTPLL_PD 14
40 #define GLCP_SYS_RSTPLL_RESETPLL 13
41 #define GLCP_SYS_RSTPLL_DDRMODE 10
42 #define GLCP_SYS_RSTPLL_VA_SEMI_SYNC_MODE 9
43 #define GLCP_SYS_RSTPLL_PCI_SEMI_SYNC_MODE 8
44 #define GLCP_SYS_RSTPLL_CHIP_RESET 0
46 /* MSR routing as follows */
47 /* MSB = 1 means not for CPU */
48 /* next 3 bits 1st port */
49 /* next3 bits next port if through an GLIU */
52 /* Redcloud as follows. */
83 #define MSR_GLIU0 (GL0_GLIU0 << 29) + (1 << 28) /* 1000xxxx - To get on GeodeLink one bit has to be set */
84 #define MSR_MC (GL0_MC << 29) /* 2000xxxx */
85 #define MSR_GLIU1 (GL0_GLIU1 << 29) /* 4000xxxx */
86 #define MSR_CPU (GL0_CPU << 29) /* 6000xxxx - this is not used for BIOS since code executing on CPU doesn't need to be routed */
87 #define MSR_VG (GL0_VG << 29) /* 8000xxxx */
88 #define MSR_GP (GL0_GP << 29) /* A000xxxx */
89 #define MSR_DF (GL0_DF << 29) /* C000xxxx */
91 #define MSR_GLCP (GL1_GLCP << 26) + MSR_GLIU1 /* 4C00xxxx */
92 #define MSR_PCI (GL1_PCI << 26) + MSR_GLIU1 /* 5000xxxx */
93 #define MSR_FG (GL1_FG << 26) + MSR_GLIU1 /* 5400xxxx */
94 #define MSR_VIP ((GL1_VIP << 26) + MSR_GLIU1) /* 5400xxxx */
95 #define MSR_AES ((GL1_AES << 26) + MSR_GLIU1) /* 5800xxxx */
98 #define SB_PORT 2 /* port of the SouthBridge */
100 /* GeodeLink Interface Unit 0 (GLIU0) port0 */
101 #define GLIU0_GLD_MSR_CAP (MSR_GLIU0 + 0x2000)
102 #define GLIU0_GLD_MSR_PM (MSR_GLIU0 + 0x2004)
104 #define GLIU0_DESC_BASE (MSR_GLIU0 + 0x20)
105 #define GLIU0_CAP (MSR_GLIU0 + 0x86)
106 #define GLIU0_GLD_MSR_COH (MSR_GLIU0 + 0x80)
108 /* Memory Controller GLIU0 port 1 */
109 #define MC_GLD_MSR_CAP (MSR_MC + 0x2000)
110 #define MC_GLD_MSR_PM (MSR_MC + 0x2004)
112 #define MC_CF07_DATA (MSR_MC + 0x18)
113 #define CF07_UPPER_D1_SZ_SHIFT 28
114 #define CF07_UPPER_D1_MB_SHIFT 24
115 #define CF07_UPPER_D1_CB_SHIFT 20
116 #define CF07_UPPER_D1_PSZ_SHIFT 16
117 #define CF07_UPPER_D0_SZ_SHIFT 12
118 #define CF07_UPPER_D0_MB_SHIFT 8
119 #define CF07_UPPER_D0_CB_SHIFT 4
120 #define CF07_UPPER_D0_PSZ_SHIFT 0
121 #define CF07_LOWER_REF_INT_SHIFT 8
122 #define CF07_LOWER_LOAD_MODE_DDR_SET (1 << 28)
123 #define CF07_LOWER_LOAD_MODE_DLL_RESET (1 << 27)
124 #define CF07_LOWER_EMR_QFC_SET (1 << 26)
125 #define CF07_LOWER_EMR_DRV_SET (1 << 25)
126 #define CF07_LOWER_REF_TEST_SET (1 << 3)
127 #define CF07_LOWER_PROG_DRAM_SET (1 << 0)
129 #define MC_CF8F_DATA (MSR_MC + 0x19)
130 #define CF8F_UPPER_XOR_BS_SHIFT 19
131 #define CF8F_UPPER_XOR_MB0_SHIFT 18
132 #define CF8F_UPPER_XOR_BA1_SHIFT 17
133 #define CF8F_UPPER_XOR_BA0_SHIFT 16
134 #define CF8F_UPPER_REORDER_DIS_SET (1 << 8)
135 #define CF8F_UPPER_REG_DIMM_SHIFT 4
136 #define CF8F_LOWER_CAS_LAT_SHIFT 28
137 #define CF8F_LOWER_REF2ACT_SHIFT 24
138 #define CF8F_LOWER_ACT2PRE_SHIFT 20
139 #define CF8F_LOWER_PRE2ACT_SHIFT 16
140 #define CF8F_LOWER_ACT2CMD_SHIFT 12
141 #define CF8F_LOWER_ACT2ACT_SHIFT 8
142 #define CF8F_UPPER_32BIT_SET (1 << 5)
143 #define CF8F_UPPER_HOI_LOI_SET (1 << 1)
145 #define MC_CF1017_DATA (MSR_MC + 0x1A)
146 #define CF1017_LOWER_PM1_UP_DLY_SET (1 << 8)
147 #define CF1017_LOWER_WR2DAT_SHIFT 0
149 #define MC_CFCLK_DBUG (MSR_MC + 0x1D)
150 #define CFCLK_UPPER_MTST_B2B_DIS_SET (1 << 2)
151 #define CFCLK_UPPER_MTST_DQS_EN_SET (1 << 1)
152 #define CFCLK_UPPER_MTEST_EN_SET (1 << 0)
153 #define CFCLK_LOWER_MASK_CKE_SET1 (1 << 9)
154 #define CFCLK_LOWER_MASK_CKE_SET0 (1 << 8)
155 #define CFCLK_LOWER_SDCLK_SET (0x0F << 0)
157 #define MC_CF_RDSYNC (MSR_MC + 0x1F)
159 /* GLIU1 GLIU0 port2 */
160 #define GLIU1_GLD_MSR_CAP (MSR_GLIU1 + 0x2000)
161 #define GLIU1_GLD_MSR_PM (MSR_GLIU1 + 0x2004)
162 #define GLIU1_GLD_MSR_COH (MSR_GLIU1 + 0x80)
164 /* CPU ; does not need routing instructions since we are executing there. */
165 #define CPU_GLD_MSR_CAP 0x2000
166 #define CPU_GLD_MSR_CONFIG 0x2001
167 #define CPU_GLD_MSR_PM 0x2004
168 #define CPU_GLD_MSR_DIAG 0x2005
169 #define DIAG_SEL1_MODE_SHIFT 16
170 #define DIAG_SEL1_SET (1 << 31)
171 #define DIAG_SEL0__MODE_SHIFT 0
172 #define DIAG_SET0_SET (1 << 15)
173 #define CPU_PF_BTB_CONF 0x1100
174 #define BTB_ENABLE_SET (1 << 0)
175 #define RETURN_STACK_ENABLE_SET (1 << 4)
176 #define CPU_PF_BTBRMA_BIST 0x110C
177 #define CPU_XC_CONFIG 0x1210
178 #define XC_CONFIG_SUSP_ON_HLT (1 << 0)
179 #define CPU_ID_CONFIG 0x1250
180 #define ID_CONFIG_SERIAL_SET (1 << 0)
181 #define CPU_AC_MSR 0x1301
182 #define CPU_EX_BIST 0x1428
185 #define CPU_IM_CONFIG 0x1700
186 #define IM_CONFIG_LOWER_ICD_SET (1 << 8)
187 #define IM_CONFIG_LOWER_QWT_SET (1 << 20)
188 #define CPU_IC_INDEX 0x1710
189 #define CPU_IC_DATA 0x1711
190 #define CPU_IC_TAG 0x1712
191 #define CPU_IC_TAG_I 0x1713
192 #define CPU_ITB_INDEX 0x1720
193 #define CPU_ITB_LRU 0x1721
194 #define CPU_ITB_ENTRY 0x1722
195 #define CPU_ITB_ENTRY_I 0x1723
196 #define CPU_IM_BIST_TAG 0x1730
197 #define CPU_IM_BIST_DATA 0x1731
199 /* various CPU MSRs */
200 #define CPU_DM_CONFIG0 0x1800
201 #define DM_CONFIG0_UPPER_WSREQ_SHIFT 12
202 #define DM_CONFIG0_LOWER_DCDIS_SET (1<<8)
203 #define DM_CONFIG0_LOWER_WBINVD_SET (1<<5)
204 #define DM_CONFIG0_LOWER_MISSER_SET (1<<1)
206 /* configuration MSRs */
207 #define CPU_RCONF_DEFAULT 0x1808
208 #define RCONF_DEFAULT_UPPER_ROMRC_SHIFT 24
209 #define RCONF_DEFAULT_UPPER_ROMBASE_SHIFT 4
210 #define RCONF_DEFAULT_UPPER_DEVRC_HI_SHIFT 0
211 #define RCONF_DEFAULT_LOWER_DEVRC_LOW_SHIFT 28
212 #define RCONF_DEFAULT_LOWER_SYSTOP_SHIFT 8
213 #define RCONF_DEFAULT_LOWER_SYSRC_SHIFT 0
214 #define CPU_RCONF_BYPASS 0x180A
215 #define CPU_RCONF_A0_BF 0x180B
216 #define CPU_RCONF_C0_DF 0x180C
217 #define CPU_RCONF_E0_FF 0x180D
218 #define CPU_RCONF_SMM 0x180E
219 #define RCONF_SMM_UPPER_SMMTOP_SHIFT 12
220 #define RCONF_SMM_UPPER_RCSMM_SHIFT 0
221 #define RCONF_SMM_LOWER_SMMBASE_SHIFT 12
222 #define RCONF_SMM_LOWER_RCNORM_SHIFT 0
223 #define RCONF_SMM_LOWER_EN_SET (1<<8)
224 #define CPU_RCONF_DMM 0x180F
225 #define RCONF_DMM_UPPER_DMMTOP_SHIFT 12
226 #define RCONF_DMM_UPPER_RCDMM_SHIFT 0
227 #define RCONF_DMM_LOWER_DMMBASE_SHIFT 12
228 #define RCONF_DMM_LOWER_RCNORM_SHIFT 0
229 #define RCONF_DMM_LOWER_EN_SET (1<<8)
231 #define CPU_RCONF0 0x1810
232 #define CPU_RCONF1 0x1811
233 #define CPU_RCONF2 0x1812
234 #define CPU_RCONF3 0x1813
235 #define CPU_RCONF4 0x1814
236 #define CPU_RCONF5 0x1815
237 #define CPU_RCONF6 0x1816
238 #define CPU_RCONF7 0x1817
239 #define CPU_CR1_MSR 0x1881
240 #define CPU_CR2_MSR 0x1882
241 #define CPU_CR3_MSR 0x1883
242 #define CPU_CR4_MSR 0x1884
243 #define CPU_DC_INDEX 0x1890
244 #define CPU_DC_DATA 0x1891
245 #define CPU_DC_TAG 0x1892
246 #define CPU_DC_TAG_I 0x1893
247 #define CPU_SNOOP 0x1894
248 #define CPU_DTB_INDEX 0x1898
249 #define CPU_DTB_LRU 0x1899
250 #define CPU_DTB_ENTRY 0x189A
251 #define CPU_DTB_ENTRY_I 0x189B
252 #define CPU_L2TB_INDEX 0x189C
253 #define CPU_L2TB_LRU 0x189D
254 #define CPU_L2TB_ENTRY 0x189E
255 #define CPU_L2TB_ENTRY_I 0x189F
256 #define CPU_DM_BIST 0x18C0
259 #define CPU_AC_SMM_CTL 0x1301
260 #define SMM_NMI_EN_SET (1<<0)
261 #define SMM_SUSP_EN_SET (1<<1)
262 #define NEST_SMI_EN_SET (1<<2)
263 #define SMM_INST_EN_SET (1<<3)
264 #define INTL_SMI_EN_SET (1<<4)
265 #define EXTL_SMI_EN_SET (1<<5)
267 #define CPU_FPU_MSR_MODE 0x1A00
268 #define FPU_IE_SET (1<<0)
270 #define CPU_FP_UROM_BIST 0x1A03
272 #define CPU_BC_CONF_0 0x1900
273 #define TSC_SUSP_SET (1<<5)
274 #define SUSP_EN_SET (1<<12)
277 #define VG_GLD_MSR_CAP (MSR_VG + 0x2000)
278 #define VG_GLD_MSR_CONFIG (MSR_VG + 0x2001)
279 #define VG_GLD_MSR_PM (MSR_VG + 0x2004)
281 #define GP_GLD_MSR_CAP (MSR_GP + 0x2000)
282 #define GP_GLD_MSR_CONFIG (MSR_GP + 0x2001)
283 #define GP_GLD_MSR_PM (MSR_GP + 0x2004)
286 #define DF_GLD_MSR_CAP (MSR_DF + 0x2000)
287 #define DF_GLD_MSR_MASTER_CONF (MSR_DF + 0x2001)
288 #define DF_LOWER_LCD_SHIFT 6
289 #define DF_GLD_MSR_PM (MSR_DF + 0x2004)
291 /* GeodeLink Control Processor GLIU1 port3 */
292 #define GLCP_GLD_MSR_CAP (MSR_GLCP + 0x2000)
293 #define GLCP_GLD_MSR_CONF (MSR_GLCP + 0x2001)
294 #define GLCP_GLD_MSR_PM (MSR_GLCP + 0x2004)
296 #define GLCP_DELAY_CONTROLS (MSR_GLCP + 0x0F)
298 #define GLCP_SYS_RSTPLL (MSR_GLCP +0x14 /* R/W */)
299 #define RSTPLL_UPPER_MDIV_SHIFT 9
300 #define RSTPLL_UPPER_VDIV_SHIFT 6
301 #define RSTPLL_UPPER_FBDIV_SHIFT 0
302 #define RSTPLL_LOWER_SWFLAGS_SHIFT 26
303 #define RSTPLL_LOWER_SWFLAGS_MASK (0x3F<<RSTPLL_LOWER_SWFLAGS_SHIFT)
304 #define RSTPPL_LOWER_HOLD_COUNT_SHIFT 16
305 #define RSTPPL_LOWER_BYPASS_SHIFT 15
306 #define RSTPPL_LOWER_TST_SHIFT 11
307 #define RSTPPL_LOWER_SDRMODE_SHIFT 10
308 #define RSTPPL_LOWER_BOOTSTRAP_SHIFT 4
309 #define RSTPPL_LOWER_LOCK_SET (1<<25)
310 #define RSTPPL_LOWER_LOCKWAIT_SET (1<<24)
311 #define RSTPPL_LOWER_BYPASS_SET (1<<15)
312 #define RSTPPL_LOWER_PD_SET (1<<14)
313 #define RSTPPL_LOWER_PLL_RESET_SET (1<<13)
314 #define RSTPPL_LOWER_SDRMODE_SET (1<<10)
315 #define RSTPPL_LOWER_CPU_SEMI_SYNC_SET (1<<9)
316 #define RSTPPL_LOWER_PCI_SEMI_SYNC_SET (1<<8)
317 #define RSTPPL_LOWER_CHIP_RESET_SET (1<<0)
319 #define GLCP_DOTPLL (MSR_GLCP + 0x15 /* R/W */)
320 #define DOTPPL_LOWER_PD_SET (1<<14)
323 #define GLPCI_GLD_MSR_CAP (MSR_PCI + 0x2000)
324 #define GLPCI_GLD_MSR_CONFIG (MSR_PCI + 0x2001)
325 #define GLPCI_GLD_MSR_PM (MSR_PCI + 0x2004)
327 #define GLPCI_CTRL (MSR_PCI + 0x2010)
328 #define GLPCI_CTRL_UPPER_FTH_SHIFT 28
329 #define GLPCI_CTRL_UPPER_RTH_SHIFT 24
330 #define GLPCI_CTRL_UPPER_SBRTH_SHIFT 20
331 #define GLPCI_CTRL_UPPER_DTL_SHIFT 14
332 #define GLPCI_CTRL_UPPER_WTO_SHIFT 11
333 #define GLPCI_CTRL_UPPER_LAT_SHIFT 3
334 #define GLPCI_CTRL_UPPER_ILTO_SHIFT 8
335 #define GLPCI_CTRL_LOWER_IRFT_SHIFT 18
336 #define GLPCI_CTRL_LOWER_IRFC_SHIFT 16
337 #define GLPCI_CTRL_LOWER_ER_SET (1<<11)
338 #define GLPCI_CTRL_LOWER_LDE_SET (1<<9)
339 #define GLPCI_CTRL_LOWER_OWC_SET (1<<4)
340 #define GLPCI_CTRL_LOWER_IWC_SET (1<<3)
341 #define GLPCI_CTRL_LOWER_PCD_SET (1<<2)
342 #define GLPCI_CTRL_LOWER_ME_SET (1<<0)
344 #define GLPCI_ARB (MSR_PCI + 0x2011)
345 #define GLPCI_ARB_UPPER_BM1_SET (1<<17)
346 #define GLPCI_ARB_UPPER_BM0_SET (1<<16)
347 #define GLPCI_ARB_UPPER_CPRE_SET (1<<15)
348 #define GLPCI_ARB_UPPER_PRE2_SET (1<<10)
349 #define GLPCI_ARB_UPPER_PRE1_SET (1<<9)
350 #define GLPCI_ARB_UPPER_PRE0_SET (1<<8)
351 #define GLPCI_ARB_UPPER_CRME_SET (1<<7)
352 #define GLPCI_ARB_UPPER_RME2_SET (1<<2)
353 #define GLPCI_ARB_UPPER_RME1_SET (1<<1)
354 #define GLPCI_ARB_UPPER_RME0_SET (1<<0)
355 #define GLPCI_ARB_LOWER_PRCM_SHIFT 24
356 #define GLPCI_ARB_LOWER_FPVEC_SHIFT 16
357 #define GLPCI_ARB_LOWER_RMT_SHIFT 6
358 #define GLPCI_ARB_LOWER_IIE_SET (1<<8)
359 #define GLPCI_ARB_LOWER_PARK_SET (1<<0)
361 #define GLPCI_REN (MSR_PCI + 0x2014)
362 #define GLPCI_A0_BF (MSR_PCI + 0x2015)
363 #define GLPCI_C0_DF (MSR_PCI + 0x2016)
364 #define GLPCI_E0_FF (MSR_PCI + 0x2017)
365 #define GLPCI_RC0 (MSR_PCI + 0x2018)
366 #define GLPCI_RC1 (MSR_PCI + 0x2019)
367 #define GLPCI_RC2 (MSR_PCI + 0x201A)
368 #define GLPCI_RC3 (MSR_PCI + 0x201B)
369 #define GLPCI_RC4 (MSR_PCI + 0x201C)
370 #define GLPCI_RC_UPPER_TOP_SHIFT 12
371 #define GLPCI_RC_LOWER_BASE_SHIFT 12
372 #define GLPCI_RC_LOWER_EN_SET (1<<8)
373 #define GLPCI_RC_LOWER_PF_SET (1<<5)
374 #define GLPCI_RC_LOWER_WC_SET (1<<4)
375 #define GLPCI_RC_LOWER_WP_SET (1<<2)
376 #define GLPCI_RC_LOWER_CD_SET (1<<0)
377 #define GLPCI_ExtMSR (MSR_PCI + 0x201E)
378 #define GLPCI_SPARE (MSR_PCI + 0x201F)
379 #define GLPCI_SPARE_LOWER_AILTO_SET (1<<6)
380 #define GLPCI_SPARE_LOWER_PPD_SET (1<<5)
381 #define GLPCI_SPARE_LOWER_PPC_SET (1<<4)
382 #define GLPCI_SPARE_LOWER_MPC_SET (1<<3)
383 #define GLPCI_SPARE_LOWER_MME_SET (1<<2)
384 #define GLPCI_SPARE_LOWER_NSE_SET (1<<1)
385 #define GLPCI_SPARE_LOWER_SUPO_SET (1<<0)
387 /* FooGlue GLIU1 port 5 */
388 #define FG_GLD_MSR_CAP (MSR_FG + 0x2000)
389 #define FG_GLD_MSR_PM (MSR_FG + 0x2004)
391 /* VIP GLIU1 port 5 */
392 #define VIP_GLD_MSR_CAP (MSR_VIP + 0x2000)
393 #define VIP_GLD_MSR_CONFIG (MSR_VIP + 0x2001)
394 #define VIP_GLD_MSR_PM (MSR_VIP + 0x2004)
395 #define VIP_BIST (MSR_VIP + 0x2005)
396 #define VIP_GIO_MSR_SEL (MSR_VIP + 0x2010)
398 /* AES GLIU1 port 6 */
399 #define AES_GLD_MSR_CAP (MSR_AES + 0x2000)
400 #define AES_GLD_MSR_CONFIG (MSR_AES + 0x2001)
401 #define AES_GLD_MSR_PM (MSR_AES + 0x2004)
402 #define AES_CONTROL (MSR_AES + 0x2006)
405 #define MIN_MOD_BANKS 1
406 #define MAX_MOD_BANKS 2
407 #define MIN_DEV_BANKS 2
408 #define MAX_DEV_BANKS 4
409 #define MAX_COL_ADDR 17
412 #define BM 1 /* Base Mask - map power of 2 size aligned region */
413 #define BMO 2 /* BM with an offset */
414 #define R 3 /* Range - 4k range minimum */
415 #define RO 4 /* R with offset */
416 #define SC 5 /* Swiss 0xCeese - maps a 256K region in to 16K 0xcunks. Set W/R */
417 #define BMIO 6 /* Base Mask IO */
418 #define SCIO 7 /* Swiss 0xCeese IO */
419 #define SC_SHADOW 8 /* Special marker for Shadow SC descriptors so setShadow proc is independant of CPU */
420 #define R_SYSMEM 9 /* Special marker for SYSMEM R descriptors so GLIUInit proc is independant of CPU */
421 #define BMO_SMM 10 /* Specail marker for SMM */
422 #define BM_SMM 11 /* Specail marker for SMM */
423 #define BMO_DMM 12 /* Specail marker for DMM */
424 #define BM_DMM 13 /* Specail marker for DMM */
425 #define RO_FB 14 /* special for Frame buffer. */
426 #define R_FB 15 /* special for FB. */
427 #define OTHER 0x0FE /* Special marker for other */
428 #define GL_END 0x0FF /* end */
430 #define MSR_GL0 (GL1_GLIU0 << 29)
432 /* Set up desc addresses from 20 - 3f */
433 /* This is chip specific! */
434 #define MSR_GLIU0_BASE1 (MSR_GLIU0 + 0x20) /* BM */
435 #define MSR_GLIU0_BASE2 (MSR_GLIU0 + 0x21) /* BM */
436 #define MSR_GLIU0_SHADOW (MSR_GLIU0 + 0x2C) /* SCO should only be SC */
437 #define MSR_GLIU0_SYSMEM (MSR_GLIU0 + 0x28) /* RO should only be R */
438 #define MSR_GLIU0_SMM (MSR_GLIU0 + 0x26) /* BMO */
439 #define MSR_GLIU0_DMM (MSR_GLIU0 + 0x27) /* BMO */
441 #define MSR_GLIU1_BASE1 (MSR_GLIU1 + 0x20) /* BM */
442 #define MSR_GLIU1_BASE2 (MSR_GLIU1 + 0x21) /* BM */
443 #define MSR_GLIU1_SHADOW (MSR_GLIU1 + 0x2D) /* SCO should only be SC */
444 #define MSR_GLIU1_SYSMEM (MSR_GLIU1 + 0x29) /* RO should only be R */
445 #define MSR_GLIU1_SMM (MSR_GLIU1 + 0x23) /* BM */
446 #define MSR_GLIU1_DMM (MSR_GLIU1 + 0x24) /* BM */
447 #define MSR_GLIU1_FPU_TRAP (MSR_GLIU1 + 0x0E3) /* FooGlue F0 for FPU */
449 /* definitions that are "once you are mostly up, start VSA" type things */
450 #define SMM_OFFSET 0x40400000
451 #define SMM_SIZE 128 /* changed SMM_SIZE from 256 KB to 128 KB */
452 #define DMM_OFFSET 0x0C0000000
454 #define FB_OFFSET 0x41000000
455 #define PCI_MEM_TOP 0x0EFFFFFFF /* Top of PCI mem allocation region */
456 #define PCI_IO_TOP 0x0EFFF /* Top of PCI I/O allocation region */
457 #define END_OPTIONROM_SPACE 0x0DFFF /* E0000 is reserved for SystemROMs */
459 #define MDD_SMBUS 0x06000 /* SMBUS IO location */
460 #define MDD_GPIO 0x06100 /* GPIO & ICF IO location */
461 #define MDD_MFGPT 0x06200 /* General Purpose Timers IO location */
462 #define MDD_IRQ_MAPPER 0x06300 /* IRQ Mapper */
463 #define ACPI_BASE 0x09C00 /* ACPI Base */
464 #define MDD_PM 0x09D00 /* Power Management Logic - placed at the end of ACPI */
466 #define CS5535_IDSEL 0x02000000 /* IDSEL = AD25, device #15 */
467 #define CHIPSET_DEV_NUM 15
468 #define IDSEL_BASE 11 /* bit 11 = device 1 */
470 /* SB LBAR IO + MEMORY MAP */
471 #define SMBUS_BASE (0x6000)
472 #define GPIO_BASE (0x6100)
473 #define MFGPT_BASE (0x6200)
474 #define IRQMAP_BASE (0x6300)
475 #define PMLogic_BASE (0x9D00)
478 #if !defined(__ROMCC__) && !defined(ASSEMBLY)
479 #if defined(__PRE_RAM__)
480 void cpuRegInit(void);
481 void SystemPreInit(void);
486 #endif /* CPU_AMD_GX2DEF_H */