2 * This file is part of the coreboot project.
4 * Copyright (C) 2011 Google Inc
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 #include <arch/romcc_io.h>
23 #include <cpu/x86/car.h>
26 #include <device/pci_def.h>
29 PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_BUS, \
30 CONFIG_OXFORD_OXPCIE_BRIDGE_DEVICE, \
31 CONFIG_OXFORD_OXPCIE_BRIDGE_FUNCTION)
33 #define OXPCIE_DEVICE \
34 PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 0)
36 #define OXPCIE_DEVICE_3 \
37 PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 3)
39 #if defined(__PRE_RAM__)
40 int oxford_oxpcie_present CAR_GLOBAL;
42 void oxford_init(void)
45 oxford_oxpcie_present = 1;
47 /* First we reset the secondary bus */
48 reg16 = pci_read_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL);
49 reg16 |= (1 << 6); /* SRESET */
50 pci_write_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL, reg16);
52 /* Assume we don't have to wait here forever */
54 /* Read back and clear reset bit. */
55 reg16 = pci_read_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL);
56 reg16 &= ~(1 << 6); /* SRESET */
57 pci_write_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL, reg16);
59 /* Set up subordinate bus number */
60 pci_write_config8(PCIE_BRIDGE, PCI_SECONDARY_BUS, 0x00);
61 pci_write_config8(PCIE_BRIDGE, PCI_SUBORDINATE_BUS, 0x00);
62 pci_write_config8(PCIE_BRIDGE, PCI_SECONDARY_BUS,
63 CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE);
64 pci_write_config8(PCIE_BRIDGE, PCI_SUBORDINATE_BUS,
65 CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE);
67 /* Memory window for the OXPCIe952 card */
68 // XXX is the calculation of base and limit corect?
69 pci_write_config32(PCIE_BRIDGE, PCI_MEMORY_BASE,
70 ((CONFIG_OXFORD_OXPCIE_BASE_ADDRESS & 0xffff0000) |
71 ((CONFIG_OXFORD_OXPCIE_BASE_ADDRESS >> 16) & 0xff00)));
73 /* Enable memory access through bridge */
74 reg16 = pci_read_config16(PCIE_BRIDGE, PCI_COMMAND);
75 reg16 |= PCI_COMMAND_MEMORY;
76 pci_write_config16(PCIE_BRIDGE, PCI_COMMAND, reg16);
78 u32 timeout = 20000; // Timeout in 10s of microseconds.
81 id = pci_read_config32(OXPCIE_DEVICE, PCI_VENDOR_ID);
82 if (!timeout-- || (id != 0 && id != 0xffffffff))
87 u32 device = OXPCIE_DEVICE; /* unknown default */
89 case 0xc1181415: /* e.g. Startech PEX1S1PMINI */
90 /* On this device function 0 is the parallel port, and
91 * function 3 is the serial port. So let's go look for
94 id = pci_read_config32(OXPCIE_DEVICE_3, PCI_VENDOR_ID);
97 device = OXPCIE_DEVICE_3;
99 case 0xc1581415: /* e.g. Startech MPEX2S952 */
100 device = OXPCIE_DEVICE;
104 oxford_oxpcie_present = 0;
108 /* Setup base address on device */
109 pci_write_config32(device, PCI_BASE_ADDRESS_0,
110 CONFIG_OXFORD_OXPCIE_BASE_ADDRESS);
112 /* Enable memory on device */
113 reg16 = pci_read_config16(device, PCI_COMMAND);
114 reg16 |= PCI_COMMAND_MEMORY;
115 pci_write_config16(device, PCI_COMMAND, reg16);
117 /* Now the UART initialization */
118 u32 uart0_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000;
120 uart8250_mem_init(uart0_base, (4000000 / CONFIG_TTYS0_BAUD));